ECE 448 Final Exam Spring 2006 May 12 2006 Part I closed books closed notes 30 minutes 30 questions 0 25 pt each total 7 5 points 1 Your name 2 List the names of at least two companies that developed special high level languages for describing behavior of reconfigurable hardware 3 List at least two features of Mitrion C that make this language suitable for development of applications that run on high performance reconfigurable supercomputers 4 List at least three problems specific to reconfigurable computers that need to be addressed while mapping an application to a reconfigurable supercomputer 5 Which company is a vendor of a programming environment that supports calling macros written in VHDL from a high level language called MAP C 6 List at least two phases of the back end design flow for ASICs 7 List four primary inputs and one primary output of the Synopsys Design Compiler Inputs Output 8 List at least two formats of a gate level netlist supported by ASIC tools 9 List at least two logic optimizations that can be used in ASICs to reduce interconnect delays caused by an excessive fanout 10 What is a purpose of clock gating 11 During the timing driven routing the circuit nets interconnects are divided into the following two groups 12 Give three examples of violations of electrical rules which are detected by ERC 13 List at least two differences between DLLs Delay Locked Loops and PLLs Phase Locked Loops that affect their effectiveness as a part of a Clock Manager in FPGAs 14 What is a major difference between Logic Elements LE in Cyclone II and Adaptive Logic Modules ALM in Stratix II 15 The size of M RAM memory block in Stratix II Altera FPGAs is equal to 16 Which feature of the FPGA configuration technologies is the most important from the point of view of space applications 17 FPGAs based on the following configuration technologies are instantly on after powerup without requiring any configuration multiple answers may be correct a b c d antifuse SRAM EEPROM FLASH 18 FPGAs based on the following technology have the shortest reconfiguration time a b c d Antifuse SRAM EEPROM FLASH 19 The primary difference between EEPROM and FLASH devices is that 20 How many look up tables are included in Xilinx Spartan 3 CLB slice Altera Cyclone II Logic Element 21 The way to make a VHDL function visible in all architectures of a given entity but invisible in architectures of any other entity is to define this function in the part of 22 Select all possible valid parameters of VHDL functions multiple answers may be correct a b c d constants variables ports signals 23 Which of the following constructs of VHDL are non synthesizable multiple answers may be correct o o o o o initializations e g SIGNAL a STD LOGIC 0 for generate multiplication of real numbers selected concurrent signal assignment with select when delays e g a b after 10 ns 24 What is wrong about the following architecture of a combinational comparator How would you correct this code ARCHITECTURE Behavior OF comparator IS BEGIN PROCESS A B BEGIN IF A B THEN AeqB 1 END IF END PROCESS END Behavior 25 What is a functional difference between a variable assignment and a sequential signal assignment 26 What is wrong about the following fragment of a VHDL architecture Process 1 PROCESS a b BEGIN y a AND b w c END PROCESS Process 2 PROCESS c d BEGIN z a AND b y c OR d END PROCESS 27 The number of clock cycles necessary to complete multiplication in the sequential shiftand add 16x16 multiplier is equal to a b c d e 1 2 16 32 256 28 A typical digital system consists of the following two major units 29 List at least three advantages of ASICs when compared to FPGAs 30 List at least three advantages of FPGAs when compared to ASICs
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