ECE 448 FPGA and ASIC Design with VHDL Spring 2007 ECE 448 Team Course Instructor Kris Gaj kgaj gmu edu Lab Instructors TAs Tuesday Wednesday sections Nghi Nguyen former MS CpE student nguyen nghi gmail com Thursday section Hoang Le MS CpE student specializing in Digital Systems Design hle7 gmu edu ECE 448 Team Division of Tasks Course Instructor Primary Responsibilities Lectures Preparing and grading exams and quizzes Coordination of work on development of new experiments Instructions for the lab experiments Coordination of work done by the TAs Enforcing consistent policies and grading standards Mid semester student satisfaction survey Resolving conflicts and providing feedback to the TAs Holding office hours ECE 448 Team Division of Tasks Lab Instructors TAs Primary Responsibilities Teaching hands on sessions on how to use software hardware and testing equipment needed for experiments Introductions to the lab experiments Grading student demonstrations and reports Holding office hours Development and testing of new lab experiments Course hours Lecture Tuesday Thursday 5 55 7 10 PM Robinson Hall A room 111 Lab Sessions Tuesday Wednesday Thursday 7 20 10 00 PM S T 2 room 203 Office hours Monday TBD room 203 Nghi Nguyen Monday 6 00 7 00 PM room 223 Kris Gaj Tuesday TBD room 203 Nghi Nguyen Tuesday 7 30 8 30 PM room 223 Kris Gaj Wednesday TBD room 203 Hoang Le Thursday 7 30 8 30 PM room 223 Kris Gaj ECE 448 Section Assignment Rules You are welcome to attend any of the multiple office hour sessions Please attend the class meetings of the other section only in case of emergency and give preference in access to the lab computers to the students attending the right section All experiment demonstrations need to be done in the presence of your TA and can be done exclusively during the class time of your section Lab Access Rules and Behavior Code Please refer to the FPGA Design Test Lab website http ece gmu edu labs fpgalab htm Grading criteria First part of the semester before the Spring break Lab experiments homework Part I individual assignments 20 Quizzes 5 Midterm exam for the lecture 10 Midterm exam for the lab 15 Second part of the semester after the Spring break Lab experiments homework Part II group assignments 20 Quizzes 5 Final exam 25 Spring 2007 Enrollment as of January 23 2007 Undeclared 1 BS in EE 11 BS in CpE 20 Digital Systems Computers Old Curriculum Color code BS EE ECE 280 PHYS 261 C or ECE 331 PHYS 265 BS CpE ECE 332 C C ECE 445 ECE 367 ECE 442 C C ECE 447 ECE 448 ECE 492 ECE 493 Digital Systems Computers Color code New Curriculum BS EE ECE 280 PHYS 261 C or ECE 331 C PHYS 265 BS CpE ECE 332 C ECE 448 ECE 445 C CS 222 ECE 492 CS 367 ECE 447 ECE 493 Transition from ECE 449 to ECE 448 starting in Spring 2006 ECE 449 NEW COURSE ECE 448 1 credit hour 4 credit hours Lab VHDL intro FPGA intro hands on tools intro experiment intro lab time Lecture Lab VHDL intro FPGA intro ASIC intro more advanced lectures on applications and platforms hands on tools intro experiment intro lab time ECE 448 FPGA and ASIC Design with VHDL Topics VHDL writing synthesizable RTL level code in VHDL writing test benches FPGAs architecture of FPGA devices tools for the computer aided design with FPGAs current FPGA families future trends High level ASIC Design standard cell implementation approach logic synthesis tools differences between FPGA standard cell ASIC design flow Applications basics of computer arithmetic applications from communications cryptography digital signal processing bioengineering etc Platforms FPGA boards microprocessor board FPGA board interfaces PCI PCI X reconfigurable computers New trends using high level programming languages to design hardware microprocessors embedded in FPGAs Tasks of the course Advanced course on digital system design with VHDL Comprehensive introduction to FPGA front end ASIC technology writing VHDL code for synthesis design using finite state machines and algorithmic state machines test benches hardware Xilinx FPGAs TSMC library of standard ASIC cells software VHDL simulators Synthesis tools Xilinx ISE Testing equipment oscilloscopes logic analyzer VHDL for Specification VHDL for Simulation VHDL for Synthesis Levels of design description Algorithmic level Register Transfer Level Logic gate level Circuit transistor level Physical layout level Level of description most suitable for synthesis Register Transfer Level RTL Design Description Combinational Logic Registers Combinational Logic VHDL Design Styles VHDL Design Styles Testbenches dataflow Concurrent statements structural Components and interconnects behavioral Sequential statements Registers State machines Subset most suitable for synthesis Testbenches Testbench Environment TB Processes Generating Stimuli All DUT Inputs Design Under Test DUT Stimuli Simulated Outputs World of Integrated Circuits Integrated Circuits Full Custom ASICs Semi Custom ASICs PLD PAL PLA User Programmable FPGA PML LUT Look Up Table MUX Gates What is an FPGA Configurable Logic Blocks Block RAMs Block RAMs I O Blocks Block RAMs Two competing implementation approaches ASIC Application Specific Integrated Circuit designed all the way from behavioral description to physical layout designs must be sent for expensive and time consuming fabrication in semiconductor foundry FPGA Field Programmable Gate Array no physical layout design design ends with a bitstream used to configure a device bought off the shelf and reconfigured by designers themselves FPGAs vs ASICs ASICs High performance FPGAs Off the shelf Low development costs Low power Short time to the market Low cost but only in high volumes Reconfigurability FPGA Design process 1 Design and implement a simple unit permitting to speed up encryption with RC5 similar cipher with fixed key set on 8031 microcontroller Unlike in the experiment 5 this time your unit has to be able to perform an encryption algorithm by itself executing 32 rounds Specification Lab Experiments VHDL description Your Source Files Library IEEE use ieee std logic 1164 all use ieee std logic unsigned all Functional simulation entity RC5 core is port clock reset encr decr in std logic data input in std logic vector 31 downto 0 data output out std logic vector 31 downto 0 out full in std logic key input in std logic vector 31 downto 0 key read out std logic end AES core Synthesis Post synthesis simulation FPGA Design process 2 Implementation Timing simulation Configuration On chip testing Simulation Tools FPGA
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