ECE 448 Lecture 3 Combinational Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading P Chu FPGA Prototyping by VHDL Examples Chapter 3 RT level combinational circuit S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 6 Combinational Circuit Building Blocks Chapter 5 5 Design of Arithmetic Circuits Using CAD Tools ECE 448 FPGA and ASIC Design with VHDL 2 VHDL Design Styles ECE 448 FPGA and ASIC Design with VHDL 3 VHDL Design Styles VHDL Design Styles Testbenches dataflow Concurrent statements structural Components and interconnects behavioral sequential Sequential statements Registers State machines Instruction decoders Subset most suitable for synthesis ECE 448 FPGA and ASIC Design with VHDL 4 Synthesizable VHDL Dataflow VHDL Design Style VHDL code synthesizable Dataflow VHDL Design Style VHDL code synthesizable ECE 448 FPGA and ASIC Design with VHDL 5 Data Flow VHDL Concurrent Statements concurrent signal assignment conditional concurrent signal assignment when else selected concurrent signal assignment with select when generate scheme for equations for generate ECE 448 FPGA and ASIC Design with VHDL 6 Modeling Wires and Buses ECE 448 FPGA and ASIC Design with VHDL 7 Signals SIGNAL a STD LOGIC a 1 wire SIGNAL b STD LOGIC VECTOR 7 DOWNTO 0 b 8 bus ECE 448 FPGA and ASIC Design with VHDL 8 Merging wires and buses a 4 b 5 10 d c SIGNAL SIGNAL SIGNAL SIGNAL a b c d STD LOGIC VECTOR 3 DOWNTO 0 STD LOGIC VECTOR 4 DOWNTO 0 STD LOGIC STD LOGIC VECTOR 9 DOWNTO 0 d a b c ECE 448 FPGA and ASIC Design with VHDL 9 Splitting buses a 4 d 10 5 b c SIGNAL SIGNAL SIGNAL SIGNAL a b c d STD LOGIC VECTOR 3 DOWNTO 0 STD LOGIC VECTOR 4 DOWNTO 0 STD LOGIC STD LOGIC VECTOR 9 DOWNTO 0 a d 9 downto 6 b d 5 downto 1 c d 0 ECE 448 FPGA and ASIC Design with VHDL 10 Combinational Circuit Building Blocks ECE 448 FPGA and ASIC Design with VHDL 11 Fixed Shifters Rotators ECE 448 FPGA and ASIC Design with VHDL 12 Fixed Shift in VHDL SIGNAL A STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL AshiftR STD LOGIC VECTOR 3 DOWNTO 0 A 3 A 2 A 1 A 0 A A 1 AshiftR 0 A 3 A 2 A 1 AshiftR ECE 448 FPGA and ASIC Design with VHDL 13 Fixed Rotation in VHDL SIGNAL A STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL ArotL STD LOGIC VECTOR 3 DOWNTO 0 A 3 A 2 A 1 A 0 A A 1 ArotL A 2 A 1 A 0 A 3 ArotL ECE 448 FPGA and ASIC Design with VHDL 14 Gates ECE 448 FPGA and ASIC Design with VHDL 15 Basic Gates AND OR NOT x1 x2 x1 x2 x1 x2 xn x1 x2 xn a AND gates x1 x2 x1 x2 x1 x2 xn x1 x2 xn b OR gates x x c NOT gate ECE 448 FPGA and ASIC Design with VHDL 16 Basic Gates NAND NOR x1 x1 x2 x2 x1 x2 xn x1 x2 xn a NAND gates x1 x1 x2 x2 x1 x2 x1 x2 xn xn b NOR gates ECE 448 FPGA and ASIC Design with VHDL 17 DeMorgan s Theorem and other symbols for NAND NOR x1 x2 x1 x1 x2 x2 a x1 x2 x1x2 x1 x2 x1 x1 x2 x2 b x1 x2 x1x2 ECE 448 FPGA and ASIC Design with VHDL 18 Basic Gates XOR x1 x2 0 0 1 1 0 1 0 1 f x1 x2 0 1 1 0 a Truth table x1 f x1 x2 x2 b Graphical symbol x1 x2 f x1 x2 c Sum of products implementation ECE 448 FPGA and ASIC Design with VHDL 19 Basic Gates XNOR x1 x2 0 0 1 1 0 1 0 1 f x1 x2 1 0 0 1 a Truth table x1 f x1 x2 x 1 x2 x2 b Graphical symbol x1 x2 f x1 x2 c Sum of products implementation ECE 448 FPGA and ASIC Design with VHDL 20 Data flow VHDL Example x y s cin cout ECE 448 FPGA and ASIC Design with VHDL 21 Data flow VHDL Example 1 LIBRARY ieee USE ieee std logic 1164 all ENTITY fulladd IS PORT x IN y IN cin IN s OUT cout OUT END fulladd ECE 448 FPGA and ASIC Design with VHDL STD LOGIC STD LOGIC STD LOGIC STD LOGIC STD LOGIC 22 Data flow VHDL Example 2 ARCHITECTURE dataflow OF fulladd IS BEGIN s x XOR y XOR cin cout x AND y OR cin AND x OR cin AND y END dataflow ECE 448 FPGA and ASIC Design with VHDL 23 Logic Operators Logic operators and or nand nor xor Logic operators precedence not xnor only in VHDL 93 Highest and or not nand nor xor xnor Lowest ECE 448 FPGA and ASIC Design with VHDL 24 No Implied Precedence Wanted y ab cd Incorrect y a and b or c and d equivalent to y a and b or c and d equivalent to y ab c d Correct y a and b or c and d ECE 448 FPGA and ASIC Design with VHDL 25 Multiplexers ECE 448 FPGA and ASIC Design with VHDL 26 2 to 1 Multiplexer s w 0 0 w 1 1 f a Graphical symbol ECE 448 FPGA and ASIC Design with VHDL s f 0 w 0 1 w 1 b Truth table 27 VHDL code for a 2 to 1 Multiplexer LIBRARY ieee USE ieee std logic 1164 all ENTITY mux2to1 IS PORT w0 w1 s IN STD LOGIC f OUT STD LOGIC END mux2to1 ARCHITECTURE dataflow OF mux2to1 IS BEGIN f w0 WHEN s 0 ELSE w1 END dataflow ECE 448 FPGA and ASIC Design with VHDL 28 Cascade of two multiplexers w 3 0 w 2 1 0 w 1 y 1 s2 s1 ECE 448 FPGA and ASIC Design with VHDL 29 VHDL code for a cascade of two multiplexers LIBRARY ieee USE ieee std logic 1164 all ENTITY mux cascade IS PORT w1 w2 w3 IN STD LOGIC s1 s2 IN STD LOGIC f OUT STD LOGIC END mux cascade ARCHITECTURE dataflow OF mux2to1 IS BEGIN f w1 WHEN s1 1 ELSE w2 WHEN s2 1 ELSE w3 END dataflow ECE 448 FPGA and ASIC Design with VHDL 30 Operators Relational operators Logic and relational operators precedence Highest Lowest not and or ECE 448 FPGA and ASIC Design with VHDL nand nor xor xnor 31 Priority of logic and relational operators compare a bc Incorrect when a b and c else equivalent to when a b and c else Correct when a b and c else ECE 448 FPGA and ASIC Design with VHDL 32 VHDL operators ECE 448 FPGA and ASIC Design with VHDL 33 4 to 1 Multiplexer s 0 s 1 w w w w s s 1 0 0 00 1 01 2 10 3 11 a Graphic symbol ECE 448 FPGA and ASIC Design with VHDL f f 0 …
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