ECE 448 Lecture 8 Finite State Machines ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 8 Synchronous Sequential Circuits Sections 8 1 8 5 ECE 448 FPGA and ASIC Design with VHDL 2 Optional Reading Sundar Rajan Essential VHDL RTL Synthesis Done Right Chapter 6 Finite State Machines ECE 448 FPGA and ASIC Design with VHDL 3 Execution Unit vs Control Unit ECE 448 FPGA and ASIC Design with VHDL 4 Structure of a Typical Digital System Data Inputs Execution Unit Datapath Control Inputs Control Signals Data Outputs ECE 448 FPGA and ASIC Design with VHDL Control Unit Control Control Outputs 5 Execution Unit Datapath Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task Examples of Resources Adders Multipliers Registers Memories etc ECE 448 FPGA and ASIC Design with VHDL 6 Control Unit Control Controls Data Movements in the Execution Unit by Switching Multiplexers and Enabling or Disabling Resources Follows Some Program or Schedule Often Implemented as Finite State Machine or collection of Finite State Machines ECE 448 FPGA and ASIC Design with VHDL 7 Finite State Machines Refresher ECE 448 FPGA and ASIC Design with VHDL 8 Finite State Machines FSMs Any Circuit with Memory Is a Finite State Machine Even computers can be viewed as huge FSMs Design of FSMs Involves Defining states Defining transitions between states Optimization minimization Manual Optimization Minimization Is Practical for Small FSMs Only ECE 448 FPGA and ASIC Design with VHDL 9 Moore FSM Output Is a Function of a Present State Only Inputs Next State function Next State clock reset Present State Present State register Output function ECE 448 FPGA and ASIC Design with VHDL Outputs 10 Mealy FSM Output Is a Function of a Present State and Inputs Inputs Next State function Next State clock reset Present State Present State register Output function ECE 448 FPGA and ASIC Design with VHDL Outputs 11 Moore Machine transition condition 1 state 1 output 1 transition condition 2 ECE 448 FPGA and ASIC Design with VHDL state 2 output 2 12 Mealy Machine transition condition 1 output 1 state 2 state 1 transition condition 2 output 2 ECE 448 FPGA and ASIC Design with VHDL 13 Moore vs Mealy FSM 1 Moore and Mealy FSMs Can Be Functionally Equivalent Equivalent Mealy FSM can be derived from Moore FSM and vice versa Mealy FSM Has Richer Description and Usually Requires Smaller Number of States Smaller circuit area ECE 448 FPGA and ASIC Design with VHDL 14 Moore vs Mealy FSM 2 Mealy FSM Computes Outputs as soon as Inputs Change Mealy FSM responds one clock cycle sooner than equivalent Moore FSM Moore FSM Has No Combinational Path Between Inputs and Outputs Moore FSM is more likely to have a shorter critical path ECE 448 FPGA and ASIC Design with VHDL 15 Moore FSM Example 1 Moore FSM that Recognizes Sequence 10 0 1 S0 0 1 reset Meaning of states S0 No elements of the sequence observed ECE 448 FPGA and ASIC Design with VHDL 0 S1 0 0 S1 1 observed 1 S2 1 S2 10 observed 16 Mealy FSM Example 1 Mealy FSM that Recognizes Sequence 10 0 0 1 0 S0 reset Meaning of states 1 0 S1 0 1 S0 No elements of the sequence observed ECE 448 FPGA and ASIC Design with VHDL S1 1 observed 17 Moore Mealy FSMs Example 1 clock input Moore Mealy 0 1 0 0 S0 S1 S2 S0 S0 S0 S1 S0 S0 S0 ECE 448 FPGA and ASIC Design with VHDL 0 18 Finite State Machines in VHDL ECE 448 FPGA and ASIC Design with VHDL 19 FSMs in VHDL Finite State Machines Can Be Easily Described With Processes Synthesis Tools Understand FSM Description If Certain Rules Are Followed State transitions should be described in a process sensitive to clock and asynchronous reset signals only Outputs described as concurrent statements outside the process ECE 448 FPGA and ASIC Design with VHDL 20 Moore FSM process clock reset Inputs Next State function Next State clock reset concurrent statements Present State Register Present State Output function Outputs ECE 448 FPGA and ASIC Design with VHDL 21 Mealy FSM process clock reset Inputs Next State function Next State clock reset Present State Present State Register concurrent statements ECE 448 FPGA and ASIC Design with VHDL Output function Outputs 22 Moore FSM Example 1 Moore FSM that Recognizes Sequence 10 0 1 S0 0 reset 1 0 S1 0 1 S2 1 0 ECE 448 FPGA and ASIC Design with VHDL 23 Moore FSM in VHDL 1 TYPE state IS S0 S1 S2 SIGNAL Moore state state U Moore PROCESS clock reset BEGIN IF reset 1 THEN Moore state S0 ELSIF clock 1 AND clock event THEN CASE Moore state IS WHEN S0 IF input 1 THEN Moore state S1 ELSE Moore state S0 END IF ECE 448 FPGA and ASIC Design with VHDL 24 Moore FSM in VHDL 2 WHEN S1 IF input 0 THEN Moore state S2 ELSE Moore state S1 END IF WHEN S2 IF input 0 THEN Moore state S0 ELSE Moore state S1 END IF END CASE END IF END PROCESS Output 1 WHEN Moore state S2 ELSE 0 ECE 448 FPGA and ASIC Design with VHDL 25 Mealy FSM Example 1 Mealy FSM that Recognizes Sequence 10 0 0 1 0 S0 reset ECE 448 FPGA and ASIC Design with VHDL 1 0 S1 0 1 26 Mealy FSM in VHDL 1 TYPE state IS S0 S1 SIGNAL Mealy state state U Mealy PROCESS clock reset BEGIN IF reset 1 THEN Mealy state S0 ELSIF clock 1 AND clock event THEN CASE Mealy state IS WHEN S0 IF input 1 THEN Mealy state S1 ELSE Mealy state S0 END IF ECE 448 FPGA and ASIC Design with VHDL 27 Mealy FSM in VHDL 2 WHEN S1 IF input 0 THEN Mealy state S0 ELSE Mealy state S1 END IF END CASE END IF END PROCESS Output 1 WHEN Mealy state S1 AND input 0 ELSE 0 ECE 448 FPGA and ASIC Design with VHDL 28 Moore FSM Example 2 State diagram resetn w 1 w 0 A z 0 B z 0 w 0 w 1 w 0 C z 1 w 1 ECE 448 FPGA and ASIC Design with VHDL 29 Moore FSM Example 2 State table Present Next state Output state w 0 w 1 z A B C A A A ECE 448 FPGA and ASIC Design with VHDL B C C 0 0 1 30 Moore FSM process clock reset Input w Next State function Next State clock resetn concurrent statements Present State Register Present State y Output function Output z ECE 448 FPGA and ASIC Design with VHDL 31 Moore FSM Example 2 VHDL code 1 USE ieee std logic 1164 all ENTITY simple IS PORT clock resetn w z END simple IN STD LOGIC IN STD LOGIC IN STD LOGIC OUT STD LOGIC ARCHITECTURE Behavior OF simple IS TYPE State type IS A B C SIGNAL y State type BEGIN PROCESS resetn clock BEGIN …
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