ECE 448 Lecture 6 FPGA devices ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading 1 S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 3 6 5 Field Programmable Gate Arrays ECE 448 FPGA and ASIC Design with VHDL 2 Required Reading 2 Xilinx Inc Spartan 3 FPGA Introduction Features Architectural Overview Package Marking Spartan 3 FPGA Functional Description CLB Overview Block RAM Overview Dedicated Multipliers Interconnect ECE 448 FPGA and ASIC Design with VHDL 3 World of Integrated Circuits Integrated Circuits Full Custom ASICs Semi Custom ASICs SPLD PAL PLA CPLD PML ECE 448 FPGA and ASIC Design with VHDL User Programmable FPGA LUT Look Up Table MUX Gates 4 Two competing implementation approaches ASIC Application Specific Integrated Circuit FPGA Field Programmable Gate Array designed all the way from behavioral description to physical layout no physical layout design design ends with a bitstream used to configure a device designs must be sent for expensive and time consuming fabrication in semiconductor foundry ECE 448 FPGA and ASIC Design with VHDL bought off the shelf and reconfigured by designers themselves 5 What is an FPGA Configurable Logic Blocks Block RAMs Block RAMs I O Blocks Block RAMs ECE 448 FPGA and ASIC Design with VHDL 6 Which Way to Go ASICs High performance FPGAs Off the shelf Low development cost Low power Short time to market Low cost in high volumes ECE 448 FPGA and ASIC Design with VHDL Reconfigurability 7 Other FPGA Advantages Manufacturing cycle for ASIC is very costly lengthy and engages lots of manpower Mistakes not detected at design time have large impact on development time and cost FPGAs are perfect for rapid prototyping of digital circuits Easy upgrades like in case of software Unique applications reconfigurable computing ECE 448 FPGA and ASIC Design with VHDL 8 Major FPGA Vendors SRAM based FPGAs Xilinx Inc Share over 60 of the market Altera Corp Atmel Lattice Semiconductor Flash antifuse FPGAs Actel Corp Quick Logic Corp ECE 448 FPGA and ASIC Design with VHDL 9 Xilinx Primary products FPGAs and the associated CAD software Programmable Logic Devices ISE Alliance and Foundation Series Design Software Main headquarters in San Jose CA Fabless Semiconductor and Software Company UMC Taiwan Xilinx acquired an equity stake in UMC in 1996 Seiko Epson Japan TSMC Taiwan ECE 448 FPGA and ASIC Design with VHDL 10 Xilinx FPGA Families Old families XC3000 XC4000 XC5200 Old 0 5 m 0 35 m and 0 25 m technology Not recommended for modern designs High performance families Virtex 0 22 m Virtex E Virtex EM 0 18 m Virtex II Virtex II PRO 0 13 m Virtex 4 0 09 m Low Cost Family Spartan XL derived from XC4000 Spartan II derived from Virtex Spartan IIE derived from Virtex E Spartan 3 ECE 448 FPGA and ASIC Design with VHDL 11 ECE 448 FPGA and ASIC Design with VHDL 12 Spartan 3 Family General Architecture ECE 448 FPGA and ASIC Design with VHDL 13 CLB Structure ECE 448 FPGA and ASIC Design with VHDL George Mason University CLB Structure ECE 448 FPGA and ASIC Design with VHDL 15 CLB Slice Structure Each slice contains two sets of the following Four input LUT Any 4 input logic function or 16 bit x 1 sync RAM SLICEM only or 16 bit shift register SLICEM only Carry Control Fast arithmetic logic Multiplier logic Multiplexer logic Storage element Latch or flip flop Set and reset True or inverted inputs Sync or async control ECE 448 FPGA and ASIC Design with VHDL 16 LUT Look Up Table Functionality x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x1 x2 x3 x4 y 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 LUT y x1 x2 x3 x4 x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 y 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 Look Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs x1 x2 y y ECE 448 FPGA and ASIC Design with VHDL 17 5 Input Functions implemented using two LUTs One CLB Slice can implement any function of 5 inputs Logic function is partitioned between two LUTs F5 multiplexer selects LUT A4 A3 LUT ROM RAM D A2 A1 WS DI F5 0 F4 A4 F3 A3 F2 A2 F1 A1 BX WS DI D 1 F5 GXOR X G LUT ROM RAM nBX BX 1 0 ECE 448 FPGA and ASIC Design with VHDL 18 5 Input Functions implemented using two LUTs X5 X4 X3 X2 X1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 Y 0 1 0 0 1 1 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 LUT OUT LUT ECE 448 FPGA and ASIC Design with VHDL 19 Distributed RAM RAM16X1S CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM Implements Single and DualPorts Cascade LUTs to increase RAM size Synchronous write Synchronous Asynchronous read Accompanying flip flops used for synchronous read D WE WCLK A0 A1 A2 A3 LUT O RAM32X1S D WE WCLK A0 A1 A2 A3 A4 LUT LUT or O RAM16X2S D0 D1 WE WCLK A0 A1 A2 A3 O0 O1 or RAM16X1D D WE WCLK A0 SPO A1 A2 A3 DPRA0 DPO DPRA1 DPRA2 DPRA3 ECE 448 FPGA and ASIC Design with VHDL 20 Shift Register LUT …
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