ECE 448 Lecture 5 Behavioral Design Style Registers Counters Shift Registers Basic Testbenches ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 7 Flip Flops Registers Counters and a Simple Processor 7 14 optional ECE 448 FPGA and ASIC Design with VHDL 2 Optional Reading Sundar Rajan Essential VHDL RTL Synthesis Done Right Chapter 4 Registers and Latches Chapter 5 Counters and Simple Arithmetic Functions see errata at http www vahana com bugs htm ECE 448 FPGA and ASIC Design with VHDL 3 Behavioral Design Style Registers Counters ECE 448 FPGA and ASIC Design with VHDL 4 What is a PROCESS A process is a sequence of instructions referred to as sequential statements The keyword PROCESS A process can be given a unique name using an optional LABEL This is followed by the keyword PROCESS The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY Hence the order of statements is important testing PROCESS BEGIN test vector 00 WAIT FOR 10 ns test vector 01 WAIT FOR 10 ns test vector 10 WAIT FOR 10 ns test vector 11 WAIT FOR 10 ns END PROCESS A process must end with the keywords END PROCESS ECE 448 FPGA and ASIC Design with VHDL 5 Anatomy of a Process OPTIONAL label PROCESS sensitivity list declaration part BEGIN statement part END PROCESS label ECE 448 FPGA and ASIC Design with VHDL 6 Statement Part Contains Sequential Statements to be Executed Each Time the Process Is Activated Analogous to Conventional Programming Languages ECE 448 FPGA and ASIC Design with VHDL 7 PROCESS with a SENSITIVITY LIST List of signals to which the process is sensitive Whenever there is an event on any of the signals in the sensitivity list the process fires Every time the process fires it will run in its entirety WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST ECE 448 FPGA and ASIC Design with VHDL label process sensitivity list declaration part begin statement part end process 8 Processes in VHDL Processes Describe Sequential Behavior Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to represent by a real circuit Not every process can be synthesized Use Processes with Caution in the Code to Be Synthesized Use Processes Freely in Testbenches ECE 448 FPGA and ASIC Design with VHDL 9 Use of Processes in the Synthesizable Code ECE 448 FPGA and ASIC Design with VHDL 10 Component Equivalent of a Process priority PROCESS clk BEGIN IF w 3 1 THEN y 11 ELSIF w 2 1 THEN y 10 ELSIF w 1 c THEN y a and b ELSE z 00 END IF END PROCESS ECE 448 FPGA and ASIC Design with VHDL clk w a b c y priority z All signals which appear on the left of signal assignment statement are outputs e g y z All signals which appear on the right of signal assignment statement or in logic expressions are inputs e g w a b c All signals which appear in the sensitivity list are inputs e g clk Note that not all inputs need to be included in the sensitivity list 11 VHDL Design Styles VHDL Design Styles dataflow Concurrent statements structural Components and interconnects behavioral Sequential statements Registers counters ECE 448 FPGA and ASIC Design with VHDL 12 Registers ECE 448 FPGA and ASIC Design with VHDL 13 D latch Truth table Graphical symbol Clock D 0 1 0 1 1 Q D Clock Q t 1 Q t 0 1 Timing diagram t1 t2 t3 t4 Clock D Q Time ECE 448 FPGA and ASIC Design with VHDL 14 D flip flop Truth table Graphical symbol D Q Clock t1 Clk D 0 1 0 1 Timing diagram t2 t3 Q t 1 0 1 Q t Q t t4 Clock D Q Time ECE 448 FPGA and ASIC Design with VHDL 15 D latch LIBRARY ieee USE ieee std logic 1164 all ENTITY latch IS PORT D Clock IN Q OUT END latch D STD LOGIC STD LOGIC Q Clock ARCHITECTURE Behavior OF latch IS BEGIN PROCESS D Clock BEGIN IF Clock 1 THEN Q D END IF END PROCESS END Behavior ECE 448 FPGA and ASIC Design with VHDL 16 D flip flop LIBRARY ieee USE ieee std logic 1164 all ENTITY flipflop IS PORT D Clock IN STD LOGIC Q OUT STD LOGIC END flipflop D Q Clock ARCHITECTURE Behavior 1 OF flipflop IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN Q D END IF END PROCESS END Behavior 1 ECE 448 FPGA and ASIC Design with VHDL 17 D flip flop LIBRARY ieee USE ieee std logic 1164 all ENTITY flipflop IS PORT D Clock IN STD LOGIC Q OUT STD LOGIC END flipflop D Q Clock ARCHITECTURE Behavior 2 OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock EVENT AND Clock 1 Q D END PROCESS END Behavior 2 ECE 448 FPGA and ASIC Design with VHDL 18 D flip flop with asynchronous reset LIBRARY ieee USE ieee std logic 1164 all ENTITY flipflop IS PORT D Resetn Clock Q END flipflop D IN OUT STD LOGIC STD LOGIC Q Clock Resetn ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS Resetn Clock BEGIN IF Resetn 0 THEN Q 0 ELSIF Clock EVENT AND Clock 1 THEN Q D END IF END PROCESS END Behavior ECE 448 FPGA and ASIC Design with VHDL 19 D flip flop with synchronous reset LIBRARY ieee USE ieee std logic 1164 all ENTITY flipflop IS PORT D Resetn Clock Q END flipflop IN OUT STD LOGIC STD LOGIC ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock EVENT AND Clock 1 IF Resetn 0 THEN Q 0 ELSE Q D END IF END PROCESS D Q Clock Resetn END Behavior ECE 448 FPGA and ASIC Design with VHDL 20 8 bit register with asynchronous reset LIBRARY ieee USE ieee std logic 1164 all ENTITY reg8 IS PORT D Resetn Clock Q END reg8 IN STD LOGIC VECTOR 7 DOWNTO 0 IN STD LOGIC OUT STD LOGIC VECTOR 7 DOWNTO 0 ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS Resetn Clock BEGIN IF Resetn 0 THEN Q 00000000 ELSIF Clock EVENT AND Clock 1 THEN Q D END IF END PROCESS END Behavior ECE 448 FPGA and ASIC Design with VHDL 8 8 Resetn D Q Clock reg8 21 N bit register with asynchronous reset LIBRARY ieee USE ieee std logic 1164 all ENTITY regn IS GENERIC N INTEGER 16 PORT D IN STD LOGIC VECTOR N 1 DOWNTO 0 Resetn Clock IN STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END regn ARCHITECTURE Behavior OF regn IS BEGIN PROCESS Resetn Clock BEGIN IF Resetn 0 THEN Q OTHERS 0 ELSIF Clock EVENT AND Clock 1 THEN Q D END IF END PROCESS END Behavior ECE 448 FPGA and ASIC Design with VHDL N N Resetn D Q Clock regn 22 N bit register with enable LIBRARY ieee USE …
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