11.3 - RISC Instruction Pipelines and Register WindowsOutlineWhat is RISC?What is RISC? (continued)11.3.1 Instruction PipelineInstruction Pipeline (continued)Instruction Pipeline stagesSlide 8Instruction Pipeline Stages (continued)Instruction Pipeline (Advantages of)Instruction Pipelines (Example of an advantage)Slide 12Instruction Pipeline (Example of an advantage)Pipeline Clock RateSlide 15Slide 16Slide 17Slide 18Speedup ratioSpeedup Ratio ExampleSlide 21Slide 22Slide 2311.3.2 Register Windowing and RenamingRegister Windowing and RenamingRegister WindowsRegister WindowSlide 28Slide 29Slide 30Register Window ExampleSlide 32Slide 33Register RenamingSlide 35Practical PerspectiveHappy Thanksgiving Day!!!11.3 - RISC Instruction 11.3 - RISC Instruction Pipelines and Register Pipelines and Register WindowsWindowsBy: Andy LeBy: Andy LeCS147 – Dr. Sin-Min LeeCS147 – Dr. Sin-Min LeeSan Jose State University, Fall San Jose State University, Fall 20032003OutlineQuick Review of RISC Instruction PipelinesRegister Windowing and RenamingPractical PerspectiveWhat is RISC?RISC is an acronym for Reduced Instruction Set ComputersAn opponent of the RISC processor is CISC which is Complex Instruction Set Computers.Goals of these 2 are to improve system performance.What is RISC? (continued)CISC and RISC differ in complexities of their instruction sets where CISC is more complex than RISC. The reduced number and complexity of instructions of the instruction sets of RISC processors are the basis for the improved performance. For example, the smaller instruction set allows a designer to implement a hardwired control unit which runs at a higher clock rate than its equivalent micro sequenced control unit.11.3.1 Instruction PipelineA pipeline is like an assembly line in which many products are being worked on simultaneously each at different station.With a RISC processor, 1 instruction is executed while the next is being decoded and its operands are being loaded while the following instruction is being fetched all at the same time.Instruction Pipeline (continued)By overlapping these operations, the CPU executes 1 instruction per clock cycle even though each instruction requires 3 cycles for fetch, decode, and execute.Instruction Pipeline stagesRecall the assembly line example. An instruction pipeline processes an instruction the same way the assembly line assembles a product (i.e. a car).Typical 4 stage pipeline:Stage 1: Fetches instruction from memory.Stage 2: Decodes instruction and fetches any required operandsStage 3: Executes instructionsStage 4: Stores resultsEach stage processes instructions simultaneously after a delay to fill the pipeline; this allows CPU to execute 1 instruction per clock cycle.Instruction Pipeline Stages (continued)Numerous stages between different CPUFirst RISC computer was an IBM 801 which used 4-stage instruction pipelineRISC II processor used 3-stagesMIPS uses 5-stage pipelineInstruction Pipeline (Advantages of)We could use several control units for processing instructions but a single pipelined control unit offers some advantagesReduces requirement of hardware pipelineEach stage performs only a portion of the pipeline stages and that no stage needs to incorporate a complete hardware control unitEach stage only needs the hardware associated with its specific task.Instruction Pipelines (Example of an advantage)The instruction-fetch stage only needs to read an instruction from memory. This stage does not need the hardware used to decode or execute instructionsSimilarly, a stage that decodes instructions does not access memory; the instruction-fetch stage has already loaded the instruction from memory into an instruction register for use at the decode stageInstruction Pipelines (Example of an advantage)Another advantage of instruction pipelines is the reduced complexity of the memory interfaceIf each stage had a complete control unit, ALL stages can access the memory and it can cause memory access conflicts in which the CPU must take care of.In general practice, RISC CPU have their memory partitioned into instruction and data modulesInstruction Pipeline (Example of an advantage)The instruction-fetch stage reads data only from the instruction memory module; at all other times, it is dealing with data in registersThe execute-instruction stage only access memory when it is reading data from the data memory module. Custom designed memory can be configured to allow simultaneous read/write access to different locations while avoiding memory access conflicts by the execute-instruction and store-results stages of the pipelinePipeline Clock RateThe clock rate of the pipeline and the CPU is limited to its slowest stage.Example: 4 stage pipeline with delays of 20ns, 20ns, 100ns, 40ns. The clock period must be at least 100ns to handle the delay at the 3rd stage (100ns). This results in a maximum clock rate of 10MHz. When ALL stages have same delay time, the pipeline will achieve maximum performancePipeline Clock RateTo improve pipeline performance, CPU designers use different number of stages in their instruction pipelines. The execute stage is divided into 2 sequential stages in some CPUs.Pipeline Clock RateRecall the 4 stage pipeline example (20,20,100,40 ns)Assume the 3rd stage (100ns) execute-instruction stage can be divided into 2 sequential stages to 50ns each.The pipeline will have 1 more additional stage totaling 5 stages with delays of 20,20,50,50, 40 ns. The clock period would be reduced to 50ns and clock frequency is doubled to 20MHzPipeline Clock RateSometimes we can use this same logic from the previous example to reduce the number of stages in a pipeline.In the 5 stage pipeline, we can combine stages 1 and 2 (20ns each) into a single stage with a delay of 40ns.Now the pipeline has 4 stages with delays of 40, 50, 50, 40ns.Combining the first 2 stages slightly reduces the hardware complexity w/o reducing clock frequency.Having 1 less stage allows the pipeline to fill and produce results starting 1 clock cycle earlier.Pipeline Clock RateThe pipeline offers significant performance improvement over non-pipelined CPU. The speedup is the ratio of the time needed to process n instructions using a non-pipelined control unit to the time needed using a pipelined control unit.Speedup ratioThe The speedupspeedup ratio (S ratio (Snn)
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