CS147 Practice Problems31. Decoder implementationA combinational circuit is specified by the following two Boolean functions:F1(A, B, C) = m(0, 3, 6)F2(A, B, C) = M(0, 4, 6, 7)Implement the circuit (F1 and F2) with a decoder constructed with NAND gates (shown below) using external NAND gates. 2. Complete the truth table describing the function of this element. Assume the data inputs are interpreted as a binary number <AB>. 3, The function F(A, B, C) defined by the truth table below is to be implemented using a 4-to-1 multiplexer. Label each input of the multiplexer with the appropriate value (0, 1, C, or C) to implement this function.4. Write the largest possible positive integer with two's complement representation: (a)in 8- bits. (b) in 4 bits (c) in n-bits.5. Describe the behaviour of the following sequential circuit by writing(a) Exicitation equations. (b) Transition equations:© Transition table and (d) State diagram.6. Consider the circuit below and the associated timing diagram. Keep inmind that the D flip-flop is triggered on the fallingclock edge.a) Complete the timing diagram for the Q output of the flip-flop.b) Complete the timing diagram for the Out output of the circuit._____ +----o< not |------+ | ----- | | _______________ | | | | | |---\ +-| D Q |--+----------|and |---------- OUT | | | |IN -----+-| C | ---------|__ / | | | | | --------------- | |____________________|TIMING DIAGRAM 1 |--| |--| |--| |--| |--| |--| |--| IN 0 _____| |_____| |_____| |_____| |_____| |_____| |_____| |_____ 1 Q 0 _____ 1 OUT 0 ___7. Derive the J-K flip flop input equations for all three J-K flip
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