INPUT/OUTPUT ORGANIZATION: InterruptsWhy we need Interrupts?Modes of Data TransferPollingWait StatesData Transfer With InterruptTypes of InterruptsExternal InterruptsInternal InterruptsSoftware InterruptsProcessing InterruptsClassificationHandlerHandler (cont.)Slide 15Slide 16Getting the Address of the Handler RoutineVectored InterruptsNon-Vectored InterruptsFor Non-vectored Interrupt Request:(a) Hardware and (b) timing for a nonvectored interrupt for a single deviceFor Vectored Interrupt Request:(A) Hardware and (B) Timing for a Vectored Interrupt for a Single DevicePrioritizing Multiple InterruptsExtension of the nonvectored InterruptPriority of Multiple nonvectored InterruptsExtension of the nonvectored Interrupt: Implementation IssuesHandling Multiple Interrupt: Daisy ChainingDaisy Chaining: Implementation IssuesHandling Multiple Interrupt: Parallel PriorityParallel PrioritySlide 32PowerPoint Presentation1INPUT/OUTPUT ORGANIZATION: InterruptsInterruptsCS 147JOKO SUTOMO2Why we need Why we need Interrupts?Interrupts?Input/output devices are slower than memory and CPU.Different device requires different amount of time from CPU.Uncertainty of when device will be ready.3Modes of Data Modes of Data TransferTransfer• Polling• Wait States• Interrupts4Continuously checking the status of a peripheral; e.g. read data from an input keyboard.Polling is relatively straightforward in design and programming with the sacrifice of system performance.PollingPolling5Wait StatesWait StatesIf a device assert wait signal, the CPU:stays in wait statesoutputting the address of I/O deviceoutputting value of control signal.6Data Transfer With Data Transfer With InterruptInterrupt1) When a peripheral is ready it sends an interrupt signal the the CPU2) The CPU stops execution of the program3) Accepts data from peripheral4) Returns to the interrupted program7Types of InterruptsTypes of InterruptsThere are three types of interrupts, each with several different uses:External InterruptsInternal InterruptsSoftware InterruptsProcedures for processing all types of interrupts are almost identical8External InterruptsExternal InterruptsUsed by CPU to interact with input/output devices; e.g. the CPU requests a data transfer and in input device asserts an interrupt when it is ready.Improve system performance by allowing the CPU to execute instructions.Also used to initiate transfers.9Internal InterruptsInternal InterruptsOccurs entirely within the CPUUsed to handle exception that occur during the execution of valid instructions; e.g:Divide by zero exceptionArithmetic overflowPage faultsInvalid instruction codes10Software InterruptsSoftware InterruptsGenerated by specific interrupt instructions in the CPU’s instruction set.These interrupt act like subrutine call statements except they always go to a specific address.11Processing Processing InterruptsInterrupts These events only occur if the interrupt is enabled.A handler (software to service the interrupt) is executed.CPU returns to where it left off in the main program.12ClassificationClassificationMaskable InterruptCan be ignored by the CPUNon-maskable InterruptCannot be disabled, always handled.CPU responds immediatelyHighest priority among interrupts13HandlerHandlerHandler is essentially a subroutine.There may be one handler routine for each interrupt or one unified handler routine for all interrupts.14HandlerHandler (cont.)If handler routine is interrupted part way through:Save the contents of internal registers of the CPUSave the state information within Control Unit15HandlerHandler (cont.)To illustrate, consider this execute routine for the LDAC instruction for the Relatively Simple CPULDAC1: DR M, PCPC+1, ARAR+1LDAC2: TR DR, DR M, PCPC+1LDAC3: AR DR, TRLDAC4: DR MLDAC5: AC DRHandlerHandler (cont.)When the CPU accesses the handler routine, the following steps are performed:• CPU pushes the current value of the program counter (PC) onto stack•CPU loads the address of the handler routine into the PC.•The handler routine then performs its tasks. When it finished, it returns to the correct location by popping the value of the PC off the stack17Getting the Address of Getting the Address of the Handler Routinethe Handler RoutineVectored InterruptsNon-vectored Interrupts18Vectored InterruptsVectored InterruptsVectored interrupts supply the CPU with information, the interrupt vector, which is used to generate the address of the handler routine for the interrupt.Useful for CPUs that receive interrupt request from several devices via the same control line.19Non-Vectored InterruptsNon-Vectored InterruptsA non-vectored interrupt uses a handler routine at a known address.CPU does not need any additional information to generate this address and access its handler routine.20For Non-vectored Interrupt For Non-vectored Interrupt Request:Request:An external device sends an interrupt to the CPU by asserting its IRQ signal.When CPU is ready, it asserts its interrupt acknowledge signal (IACK),The device sets IRQ low, which cause CPU to set IACK low.Handler routine proceeds and starts transferring data.21(a) Hardware and (b) timing for a nonvectored interrupt for a single device22For Vectored Interrupt Request:For Vectored Interrupt Request:External device sends interrupt to the CPU by asserting its IRQ signal.CPU inputs an interrupt vector from the device and call an interrupt service routine (handler)The device sets IRQ lowHandler routine proceeds and starts transferring data.23(A) Hardware and (B) Timing for a Vectored Interrupt for a Single Device24Prioritizing Multiple Prioritizing Multiple InterruptsInterruptsExtension of the nonvectored interrupt hardwareDaisy chainingParallel priority25Extension of the nonvectored Extension of the nonvectored InterruptInterruptHardware for multiple nonvectored interrupts26Priority of MultiplePriority of Multiplenonvectored Interruptsnonvectored InterruptsIRQn has the highest priority and IRQ0 has the lowest.E.g. IRQ 7 Has higher priority than IRQ 5.27Extension of the nonvectored Extension of the nonvectored Interrupt:Interrupt:Implementation IssuesThis method works well when there are only a few IRQ/IACK pairs.Number of pins needed by CPU to accommodate signals become prohibitive.28Handling Multiple Handling
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