CHAPTER TEN | INPUT/OUTPUTINTRODUCTIONDATA TRANSFERSPowerPoint PresentationHANDSHAKINGSlide 6INTERRUPTSexternalinternalsoftwarePROCESSINGDIRECT MEMORY ACCESS[illustration]burst modecycle-stealing modetransparentI/O PROCESSORSSlide 18SERIAL COMMUNICATIONCONCLUSIONCHAPTER TEN | INPUT/OUTPUTINTRODUCTIONusually occur when peripherals are located within the same computer as the CPU because their close proximity allows them to share a common clock and because data doesn’t have to travel very far physically, which becomes a concern at higher clock frequencies. uses control signals and their associated hardware to coordinate the movement of data. These data transfers do not require that the source and destination use the same system clock. There are four types of asynchronous data transfers, distinguished by whether the source or destination initiates the transfer, and by whether or not handshaking is used. DATA TRANSFERS• Source inputs its data, then strobes a control signal for a set amount of time.• Destination device reads in the data during this time.• Source then deasserts the strobe and stops outputting data.• Destination device transmits a data strobe signal to the source device, which after a brief delay, makes data available.• After a set delay to ensure that valid data is ready, the destination device reads in this data and deasserts the data strobe, causing the source to stop transmitting the dataThe aforementioned data transfers are appropriate for devices that occur within a set amount of time, but aren’t necessarily applicable to devices that don’t require the same amount of time for every transfer. These devices use handshaking to coordinate their transfers.HANDSHAKINGSource sets data request signal high and then makes valid data available to destination device. After a delay to allow the data to stabilize, the destination device reads in the data. Once the destination device has read the data, it sends a data-acknowledge signal to the source.Analogous to source-initiated data transfer except that the data acknowledge signal is replace with a data-ready signal.A mechanism for alleviating the delay caused by the uncertainty of when devices will be ready and for maximizing system performance…• External Interrupts• Internal Interrupts• Software InterruptsINTERRUPTSExternal interrupts are used by the CPU to interact with I/O devices. External interrupts improve system performance by allowing the CPU to execute instructions, instead of just waiting for the I/O device, while still performing the required data transfers. External interrupts can also be used to initiate transfers, rather than to signal event completion.externalInternal interrupts occur entirely within the CPU; no I/O devices play any role in these interrupts. Some interrupts in this class are purposely introduced as part of the system’s function. Internal interrupts can also be used to handle exceptions that occur during the execution of valid instructions.internalSoftware interrupts are generated by specific interrupt instructions in the CPU’s instruction set. They act like subroutine call statements except they always go to a specific address; so they do not explicitly specify the address of the handler routines.softwareAn interrupt triggers a sequence of events to occur within the computer system. These events acknowledge the interrupt and perform the actions necessary to service the interrupt. These events only occur if the interrupt is enabled. The software service to the interrupt is called the handler, essentially a subroutine. Regardless of the configuration of the handler routine(s), each interrupt is followed by the following sequence of events:• Do Nothing(until the current instruction has been executed)• Get the Address of the Handler(vectored interrupts only)• Invoke the Handler RoutinePROCESSINGAllows us to bypass the CPU and transfer data directly from the I/O device to memory.A DMA controller implements direct memory access in a computer system. It connects directly to the I/O device at one end and to the system buses at the other end. It also interacts with the CPU, both via the system buses and two new direct connections. To transfer data between an I/O device and memory, the DMA controller requests control of the system buses, and once in control, performs the desired data transfers. Once done, the DMA controller no longer needs to use the system buses so it gives control back to the CPU.DIRECT MEMORY ACCESS[illustration]In Burst Mode, an entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system buses by the CPU, it transfers all bytes of data in the data block before relinquishing control of the system buses back to the CPU. This mode is useful for loading programs or data files into memory, but renders the CPU inactive for relatively long periods of time.burst modeCycle Stealing is used for system in which the CPU should not be disabled for the length of time needed for burst transfer modes. In cycle stealing, the DMA controller obtains access to the system buses as in burst mode, however, it transfers one byte of data and then returns the control of the system buses to the CPU. It continually issues requests, transferring one byte of data per request, until it has transferred its entire block of data. The data block is not transferred as quickly as in burst mode, but the CPU is not idled for as long as in that mode. cycle-stealing modeTransparent mode requires the most time to transfer a block of data, yet it is also the most efficient in terms of overall system performance. In transparent mode, the DMA controller only transfers data when the CPU is performing operations that do not use the system buses. The primary advantage of transparent mode is that the CPU never stops executing its programs. The DMA transfer is free in terms of time. However, the hardware needed to determine when the CPU is not using the system buses can be quite complex and relatively expensive. In addition, more advanced CPUs overlap their internal operations and use the system bus almost every cycle. For these reasons, this mode is generally not used in spite of its performance advantages.transparentDMA controllers are only capable of transferring data, and in some cases, data needs to be manipulated once it is read from the I/O device, which introduces the need for I/O processors, which essentially perform the same
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