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SJSU CS 147 - RISC vs. CISC

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RISC vs. CISCCISCCISC ExamplesPro’sCon’sThe CISC ApproachRISCRISC ExamplesPro’sThe RISC ApproachPerformanceSlide 12RISC vs. CISCBy Chiam D CookCs 147 spring 08CISC•Complex Instruction Set Computer–Large number of complex instructions–Low level–Facilitate the extensive manipulation of low-level computational elements and events such as memory, binary arithmetic, and addressing.CISC Examples•Examples of CISC processors are the –System/360(excluding the 'scientific' Model 44), –VAX, –PDP-11, –Motorola 68000 family–Intel x86 architecture based processors.Pro’s • Emphasis on hardware •Includes multi-clock complex instructions •Memory-to-memory:"LOAD" and "STORE"incorporated in instructions •Small code sizes,high cycles per second •Transistors used for storingcomplex instructionsCon’s•That is, the incorporation of older instruction sets into new generations of processors tended to force growing complexity.• Many specialized CISC instructions were not used frequently enough to justify their existence. • Because each CISC command must be translated by the processor into tens or even hundreds of lines of microcode, it tends to run slower than an equivalent series of simpler commands that do not require so much translation.The CISC Approach•MULT 2:3, 5:2RISC•Reduced Instruction Set Computer–Small number of instructions–instruction size constant–bans the indirect addressing mode –retains only those instructions that can be overlapped and made to execute in one machine cycle or less.RISC Examples•Apple iPods (custom ARM7TDMI SoC)•Apple iPhone (Samsung ARM1176JZF)•Palm and PocketPC PDAs and smartphones (Intel XScale family, Samsung SC32442 - ARM9)•Nintendo Game Boy Advance (ARM7)•Nintendo DS (ARM7, ARM9)•Sony Network Walkman (Sony in-house ARM based chip)•Some Nokia and Sony Ericsson mobile phonesPro’s•Emphasis on software •Single-clock,reduced instruction only •Register to register:"LOAD" and "STORE"are independent instructions •Low cycles per second,large code sizes •Spends more transistorson memory registersThe RISC Approach•LOAD A, 2:3LOAD B, 5:2PROD A, BSTORE 2:3, APerformancePerformance•The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per


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SJSU CS 147 - RISC vs. CISC

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Cache

Cache

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Memory

Memory

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Memory

Memory

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Lecture 1

Lecture 1

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Cisc

Cisc

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Quiz 1

Quiz 1

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LECTURE 2

LECTURE 2

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RISC

RISC

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LECTURE 2

LECTURE 2

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Lecture 2

Lecture 2

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Lecture1

Lecture1

53 pages

Chapter 5

Chapter 5

14 pages

Memory

Memory

27 pages

Counters

Counters

62 pages

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