Slide 1Systems OverviewMemory width and lengthOne Bit (One Shot) StorageBetter One Bit StorageTypes of MemoryStatic Memory (SRAM)Frequency DivisionDynamic Memory (DRAM) AdvantagesDynamic Memory (DRAM) DisadvantagesOne Bit DRAMOne Bit DRAM WriteOne Bit DRAM ReadDRAM ArrayDRAM Array One Bit ReadDRAM Array Row RefreshDynamic Memory (DRAM) Techniques/ImprovementsDRAM Physical Package (and the kitchen sink)Systems OverviewSystems OverviewComputer is composed of three main components:•CPU•Main memory•IO devicesRefers to page 48-51 2Memory width and Memory width and lengthlengthMemory width: Number of bits stored in each memory register (dictated by width of system bus).Memory length: Number of registers.Refers to page 64 3WidthLength2width = max lengthOne Bit (One Shot) One Bit (One Shot) StorageStorageAND-gateRefers to page 118 401 10101Better One Bit StorageBetter One Bit StorageLatch•Multiple implementations available (S-R, J-K, D, T, 2NOR)•Q can be set, cleared, and remember in-betweenRefers to page 118 5SRQQ’Qt S R Qt+10 0 0 00 0 1 00 1 0 11 0 0 11 1 0 11 0 1 0Types of MemoryTypes of MemoryMemory TypeAccess SpeedRead/Write/RewriteDRAM 50ns Yes - Read and Write many timesSRAM 10ns Yes - Read and Write many timesROM Write OncePROM Write OnceEPROM 150ns UV erasable PROM (UV window)EEPROM Electrically erasable PROM (high voltage)FLASH Reprogrammable, non-volatileRefers to page 120 6Static Memory (SRAM)Static Memory (SRAM)•Lots of Flip-Flops•Fast (<10ns read cycles)•Expensive (only used in fast cache)•Often “byte-wide” – read one byte at a time•Frequency divisionRefers to page 121 7Frequency DivisionFrequency DivisionRefers to page 121 8Three positive-edge triggered T (toggle) Flip-Flops1ClockClockf/2f/41 1Dynamic Memory (DRAM)Dynamic Memory (DRAM)AdvantagesAdvantages•Single bit storage is a FET and a ~20fF capacitor•Equivalent storage of SRAM in ¼ area.•Read speeds of 5-50nsRefers to page 122-123 9Dynamic Memory (DRAM)Dynamic Memory (DRAM)DisadvantagesDisadvantages•“Leaky” – loses data unless refreshed (100x a second).•Read speeds of 5-50ns….but “rest” period means average read speed of 100ns (10 million reads a second).•Recovery period needed for bit lines, a delay known as cycle time.Refers to page 122-123 10One Bit DRAMOne Bit DRAMRefers to page 122 11Word line acts like electrical switchBit line writes byteCapacitor stores last written bitOne Bit DRAM WriteOne Bit DRAM WriteRefers to page 122 121. Close switch to specify what bit2. Write “1” 13. Open switch to store bitOne Bit DRAM ReadOne Bit DRAM ReadRefers to page 122 131. Close switch to specify what bit2. Read bit (in this case, 1) 1DRAM ArrayDRAM ArrayRefers to page 123 14Word Line 1Word Line 2Bit Line 1 Bit Line 2DRAM Array One Bit ReadDRAM Array One Bit ReadRefers to page 123 151. Pick this bit to read.12. Close Word Line 2 Switch(Row Address Select)3. Read Bit Line 2(Column Address Select)DRAM Array Row RefreshDRAM Array Row RefreshRefers to page 123 161. Close Word Line 2 Switch2. Read all bits to memory...and 3. amplify and rewrite back to appropriate bits.Dynamic Memory (DRAM)Dynamic Memory (DRAM)Techniques/ImprovementTechniques/Improvementss•Interleave read operations – read from “even” bank, then “odd” bank, allowing recovery time to take place during read of opposing bank.•EDO – Extended Data Output means 4 consecutive column reads for each row address select.•SDRAM- Synchronous burst (only send one address, then use on-chip CAS), self-refreshing, selectable burst lengths. Refers to page 126 17DRAM Physical PackageDRAM Physical Package(and the kitchen sink)(and the kitchen sink)•SIMM – Single Inline Memory Module•DIMM – Dual Inline Memory Module•Small cards with 8-9 DRAM chips (if 9, it’s for parity checking)•Available in 256MByte, 512Mbyte, 1GByte (and 2GByte)•Each memory cell on each chip contains 8 bits so 8x8=64 bits read every 10ns. Pentium 64 bus can use 16bits each transfer, so each 16bit instruction available every 10/4ns.•Voltage used on chips is falling from logic 5V to 2.5VRefers to page 126
View Full Document
Unlocking...