RISCAgendaOverviewSlide 4Applications of RISC (MIPS)Other companies that use MIPSSide NoteCISCExample of CISCSpecial note on Intel P4 HT+XOverview and Side noteSlide 12In GeneralPropagation DelayExampleIncrease CPU speedTradeoffCommon Features of RISC (10 of them)Common Features of RISCSlide 20Slide 21Slide 22Slide 23Slide 24Slide 25Instruction PipelineSlide 27Slide 28Slide 29Slide 30Register Windowing and RenamingSlide 32Slide 33Data ConflictsData Conflicts ExampleSlide 36Slide 37Branch Conflicts ExampleSlide 39ConclusionRISCBy Ryan AldanaAgenda•Brief Overview of RISC and CISC•Features of RISC•Instruction Pipeline•Register Windowing and renaming•Data Conflicts•Branch ConflictsOverview•The world of microprocessors is divided into 2 parts–RISC–CISCRISC•Reduced Instruction Set Computer–Instruction set is reduced•Excludes the instruction set that corresponds to higher level languages–Instruction set is simpler–RISC has under 100 instructions–Examples of RISC:•MIPS, SPARC, ARMApplications of RISC (MIPS)•“Sony Computer Entertainment Inc. (SCEI) has long relied on the MIPS® architecture, most notably for its PlayStation® family of products, including the 128-bit Emotion Engine® multimedia processor in the PlayStation® 2 computer entertainment system. In 2002, SCEI acquired a license for the MIPS64™ architecture.”text from http://www.mips.com/content/Ecosystem/Licensees/ProductCatalog/licenseesOther companies that use MIPS•ATI•Motorola•NEC•Phillips•Sharp•Sony•Texas Instruments•Toshiba–Info taken from http://www.mips.com/content/Ecosystem/Licensees/ProductCatalog/licenseesSide Note•The first microprocessors had very simple instruction setsCISC•Complex Instruction Set Computers•Instruction set is larger–Usually corresponds to statements in higher level languages•Instruction set is more complex•Example of CISC–PentiumExample of CISC•Pentium–Info and pics taken from http://www.intel.com/products/desktop/processors/pentium4HTXE/index.htm?iid=ipp_desk+proc_p4htxe&Special note on Intel P4 HT+X•Cache–“L3: 2MB, L2: 512KB, L1: 8KB”–Info and pics taken from http://www.intel.com/products/desktop/processors/pentium4HTXE/index.htm?iid=ipp_desk+proc_p4htxe&Overview and Side note•RISC and CISC have opposite approaches–Each approach offers some advantage•RISC and CISC differ in complexities of their instruction setsCISC•CISC has over 300 instructions–Some are used a lot•Like the register move instructions–Some are rarely usedIn General•The more instructions it has, the larger the propagation delay getsPropagation Delay•“The time it takes to transmit a signal from one place to another. Propagation delay is dependent solely on distance and two thirds the speed of light. Signals going through a wire or fiber generally travel at two thirds the speed of light. Contrast with nodal processing delay.”•Info taken from http://www.techweb.com/encyclopedia/defineterm?term=PROPAGATIONDELAY&exact=1Example•CPU with 16 instructions–Uses a 4-16 decoder•CPU with 32 instructions–Uses a 5-32 decoder•This decoder needs more time to generate its outputs than the smaller one •So why not use two 4-16 decoders?•Because two 4-16 decoders actually increase propagation delayIncrease CPU speed•Some designers wanted to make the CPU faster–To do that, they believed that they should reduce the propagation delay•To do that, they eliminated the rarely used instructionsTradeoff•Eliminating the instructions that corresponds to higher level language will force the processor to use more statements.–This will cause the processor to take more time to process.Common Features of RISC (10 of them)•1) Fixed length instructions–Every instruction has the same size bits•2) Limited Loading and Storing Instructions Access Memory –CISC can interact with the values in memory–RISC limits the interaction by placing the values into a register first before interactionCommon Features of RISC•3)Fewer Addressing Modes–Certain modes degrade performance•Indirect address mode–RISC has quicker addressing modes•Register Direct addressing mode•Relative addressing modeCommon Features of RISC•4)Instruction Pipeline–RISC processors can execute one instruction while fetching and decoding the next instruction–The instruction pipeline breaks up the execution into stagesCommon Features of RISC•5) Large Number of Registers–CISC uses their chip space for the control logic–RISC uses their chip space for more registers•6) Hardwired Control Unit–CISC is too complicated to implement a hardwired control unit–RISC has a hardwired control unit for higher clock ratesCommon Features of RISC•7) Delayed loads and branches–This is used to avoid wasting time•The RISC instruction pipeline encounters hazards during instructions that use a common operand–Delayed loads and branches can avoid these hazardsCommon Features of RISC•8) Speculative Execution of Instructions–The processor will execute the instruction ahead of time but not save the value•If the processor was suppose to execute the instruction, it will save the value•If not, it will discard the value•The Pentium Itanium Processor uses this methodCommon Features of RISC•9) Optimizing Compiler–An optimizing compiler can optimize the instructions to facilitate delayed loads and branches –It optimizes by rearranging the instructions to be executedCommon Features of RISC•10) Separate Instruction and Data Streams–This helps to avoid memory access conflictsInstruction Pipeline•Pipelined instructions break down the fetch-decode-execute and processes several instructions in parallel •Instruction pipeline allows RISC processors to execute one instruction per clock cycleInstruction Pipeline•The pipeline is broken down into stages–For example:•Stage 1 – fetch•Stage 2 – decode•Stage 3 – execute•Stage 4 – store value•There is latency due to initializationInstruction Pipeline•The first RISC computer uses a four stage instruction pipeline•The RISC II uses a three stage instruction pipeline•The MIPS uses a five-stage instruction pipeline•The fewer number of stages, the faster it isInstruction Pipeline•The breakdown of the instruction execution into stages reduces hardware–The fetch stage does not require the hardware needed to decode the instruction–The decode stage does not access memory because the fetch
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