SJSU CS 147 - Cache Memory (57 pages)

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Cache Memory



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Cache Memory

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Lecture Notes


Pages:
57
School:
San Jose State University
Course:
Cs 147 - Computer Architecture
Computer Architecture Documents

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Cache memory Prof Sin Min Lee Department of Computer Science Using T Flip Flop and JK Flip Flop log24 2 so 2 flip flops are needed to implement this FSA Step 1 Translate diagram into State Table Step 2 Create maps for T and JK Step 3 Determine T J and K equations Step 4 Draw resulting diagram Implementing FSM with No Inputs Using D T and JK Flip Flops Convert the diagram into a chart Implementing FSM with No Inputs Using D T and JK Flip Flops Cont For D and T Flip Flops Implementing FSM with No Inputs Using D T and JK Flip Flops Cont For JK Flip Flop Implementing FSM with No Inputs Using D T and JK Flip Flops Cont Final Implementation The Processor Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Processor Memory Bus PCI Bus I O Busses von Neumann Architecture Princeton Address Pointer Arithmetic Logic Unit ALU Data Instructions Memory Pc Pc 1 Program Counter Featuring Deterministic Execution Cache Memory Physical memory is slow more than 30 times slower than processor Cache memory uses SRAM chips Much faster Much expensive Situated closest to the processor Can be arranged hierarchically L1 cache is incorporated into processor L2 cache is outside Cache Memory This photo shows level 2 cache memory on the Processor board beside the CPU Cache Memory Three Levels Architecture Memory MultiGigabytes 2 Gigahertz Clock Cache Control Logic 2X 8X L1 Cache Memory L2 Cache Memory 32 Kilobytes Large and Slow 160 X 16X L3 Cache Memory 128 Kilobytes 16 Megabytes Featuring Really Non Deterministic Execution Address Pointer Cache 1 Is the first level of memory hierarchy encountered once the address leaves the CPU Since the principle of locality applies and taking advantage of locality to improve performance is so popular the term cache is now applied whenever buffering is employed to reuse commonly occurring items We will study caches by trying to answer the four questions for the first level of the memory hierarchy Cache 2 Every



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