PowerPoint PresentationSlide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 2301/14/19 1 RISC: Reduced Instruction Set Computer CS147Prof. Sin-Min Lee submitted by Yangcha K. Ho 3/22/0501/14/19 2 Reduced Instruction Set Computer (RISC) :• A type of microprocessor architecture • Utilizes a small, highly-optimized set of instruction.01/14/19 3 History • Started in the late 70s from IBM, Stanford, and UC-Bnerkeley.• The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with RISC features.01/14/19 4 Characteristics of RISC Processors:•Simple instructions and few addressing modes: the instruction set contains simple, basic instructions, from which more complex instructions can be composed.Each instruction is the same length, so that it may be fetched in a single operation.01/14/19 5Characteristics of most RISC Processors:(cont.)• Once Cycle execution time: RISC processors have a CPI(Clock per instruction) of one cycle. This is due to the optimization of each instruction of the CPU and a technique called “PIPELINING”.01/14/19 6 Characteristics of most RISC Processors: (cont.)• Most instructions complete in one machine cycle, which allows the processor to handle several instructions at the same time. • This pipelining is a key technique used to speed up RISC machine.01/14/19 7Characteristics of most RISC Processors: (cont.)•Use large number of registers to prevent in large number of interactions with memory. • Deep pipelining • Reliance on optimizing compilers • High-performance memory hierarchy01/14/19 8 Pipelining definitions•Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. •It is not visible to the programmer! •Each step is called a pipe stage or pipe segment.01/14/19 9 Pipelining definitions (cont.)Pipeline machine cycle: time required to move an instruction one step down the pipeline. •Throughput of an pipeline: number of instructions that can leave the pipeline each cycle.01/14/19 10 Pipelining definitions (cont.)Latency is the time needed for an instruction to pass through all pipeline stages.01/14/19 11 Basic pipeline steps Instruction fetch (IF): The instruction pointed to by the PC is fetched from memory into the instruction register of the CPU. The PC is incremented to point to the next instruction in the memory.01/14/19 12 Basic pipeline steps (conti.)•Instruction decode/register fetch (ID):The instruction is decodedIn the second half of the stage the operands are transferred from the register file into the ALU input registers.01/14/19 13Performance Issues in Pipelined systems:Reasons for stalling:1. Delays in reading information from memory2. A poor instruction set design3. Dependencies between instructions.01/14/19 14Memory Issues in Pipelined systems:Memory speed issues are commonly solved using caches. A Cache is a section of a fast memory placed between the processor and slower memory.01/14/19 15 Memory Issues (conti.) When the processor wants to read a location in main memory, that location is also copied into the cache. Subsequent references to that location can come from the cache which will return a result much more quickly than the main memory.01/14/19 16Instruction Latency:A poorly designed instruction set can causea pipelined processor to stall frequently. Examples:1. Highly encoded instructions.2. Variable length instructions which require multiple references to memory to fetch in the entire instruction.01/14/19 17 Instruction Latency:3. Instructions which access main memory( instead of registers) since main memory can be slow.4. Instructions which need to read and write the same Register.5. Dependence on single point resources such as a condition code register.01/14/19 18 Dependencies:Each instruction takes some time to store itsresult, and several instructions are being handled at the same time, later instructions may have to wait for the results of earlierinstructions to be stored. Some rearrangement of the instructions in a Program can remove these performance limitations.01/14/19 19Advantage of RISC:A processor with a simplified instruction set design provides several advantages over implementing a comparable CISC design.1. Speed. A simplified instruction set allows RISC processors often achieve 2 to 4 times faster compared to CISC processors.01/14/19 20 Advantage of RISC:2. Simpler hardware. Since the instruction set is so simple, it uses up much less chip space; extra functions, such as floating point arithmetic units, can also be placed on the same chip.Smaller chips allow a semiconductor manufacturer to place more parts on a singlesilicon wafer, which results in per-chip cost.01/14/19 21 Key issues when moving code from CISC processor to RISC processor:1. Code. The performance of a RISC processor depends greatly on the code that it is executing. If the programmer(or compiler) does a poor Job of instruction scheduling, the processor can spend quite a bit of time stalling.01/14/19 22Key issues when moving code from CISC processor to RISC processor:2. System. RISC based systems typically contain large memory caches, usually on the chip itself.01/14/19 23 Bibliographies:1. Prof. Sin-Min Lin Web site: http://www.cs.sjsu.edu/~lee/cs147/ cs147.htm2. Web site: http://www.masterliness.com/a/RISC.htm3. Web site: http://www.realworldtech.com/page.cfm? ArticleID=RWT0213000000004. Mano, M. Morris, Logig and Computer Design Fundamentals, Pearson Prentics Hall, e20045. Comer, Douglas E., Essentials of Computer
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