DIRECT MEMORY ACCESSOVERVIEWDirect Memory AccessComputer System with DMAPowerPoint PresentationSlide 6Implementing DMA in a Computer SystemData Transfer using DMA ControllerInternal ConfigurationInternal Configuration of DMA ControllerProcess of DMA TransferSlide 13DMA Transfer ModesSlide 15Slide 16Slide 17Slide 18Modification of the CPU to work with DMAHardare Implementation of BGSlide 21Modified State Diagram To Accommodate BR and BGSlide 23Slide 24SummaryDIRECT MEMORY DIRECT MEMORY ACCESSACCESSCS 147CS 147Thursday July 5,2001Thursday July 5,2001SEEMA RAISEEMA RAIOVERVIEW OVERVIEW IntroductionIntroductionImplementing DMA in a computer systemImplementing DMA in a computer systemData transfer using DMA controllerData transfer using DMA controllerInternal configuration of a DMA controllerInternal configuration of a DMA controllerProcess of DMA transferProcess of DMA transferDMA transfer modesDMA transfer modesModification of the CPU to work with DMAModification of the CPU to work with DMASummarySummaryDirect Memory AccessDirect Memory AccessIntroductionIntroductionAn important aspect governing the An important aspect governing the Computer System performance is the Computer System performance is the transfer of data between memory and I/O transfer of data between memory and I/O devices.devices.The operation involves loading programs or The operation involves loading programs or data files from disk into memory, saving file data files from disk into memory, saving file on disk, and accessing virtual memory on disk, and accessing virtual memory pages on any secondary storage medium.pages on any secondary storage medium.contcontComputer System with Computer System with DMADMAConsider a typical system consisting of a CPU Consider a typical system consisting of a CPU ,memory and one or more input/output ,memory and one or more input/output devices as shown in fig. Assume one of the devices as shown in fig. Assume one of the I/O devices is a disk drive and that the I/O devices is a disk drive and that the computer must load a program from this computer must load a program from this drive into memory.drive into memory.The CPU would read the first byte of the The CPU would read the first byte of the program and then write that byte to memory. program and then write that byte to memory. Then it would do the same for the second Then it would do the same for the second byte, until it had loaded the entire program byte, until it had loaded the entire program into memory. into memory. contcontThis process proves to be inefficient. This process proves to be inefficient. Loading data into, and then writing data out Loading data into, and then writing data out of the CPU significantly slows down the of the CPU significantly slows down the transfer. The CPU does not modify the data transfer. The CPU does not modify the data at all, so it only serves as an additional stop at all, so it only serves as an additional stop for data on the way to it’s final destinaion.for data on the way to it’s final destinaion.The process would be much quicker if we The process would be much quicker if we could bypass the CPU & transfer data could bypass the CPU & transfer data directly from the I/O device to memory.directly from the I/O device to memory.Direct Memory Access does exactly that.Direct Memory Access does exactly that.Implementing DMA in a Implementing DMA in a Computer SystemComputer SystemA DMA controller implements direct memory A DMA controller implements direct memory access in a computer system.access in a computer system.It connects directly to the I/O device at one It connects directly to the I/O device at one end and to the system buses at the other end and to the system buses at the other end. It also interacts with the CPU, both via end. It also interacts with the CPU, both via the system buses and two new direct the system buses and two new direct connections.connections. It is sometimes referred to as a channel. In It is sometimes referred to as a channel. In an alternate configuration, the DMA an alternate configuration, the DMA controller may be incorporated directly into controller may be incorporated directly into the I/O device.the I/O device.Data Transfer using DMA Data Transfer using DMA ControllerControllerTo transfer data from an I/O device to To transfer data from an I/O device to memory, the DMA controller first sends a Bus memory, the DMA controller first sends a Bus Request to the CPU by setting BR to 1. When Request to the CPU by setting BR to 1. When it is ready to grant this request, the CPU sets it is ready to grant this request, the CPU sets it’s Bus grant signal, BG to 1.it’s Bus grant signal, BG to 1.The CPU also tri-states it’s address,data, and The CPU also tri-states it’s address,data, and control lines thus truly granting control of the control lines thus truly granting control of the system buses to the DMA controller.system buses to the DMA controller.The CPU will continue to tri-state it’s outputs The CPU will continue to tri-state it’s outputs as long as BR is asserted. as long as BR is asserted. contcontInternal Internal ConfigurationConfigurationThe DMA controller includes several registers :-The DMA controller includes several registers :-•The DMA Address Register contains the memory The DMA Address Register contains the memory address to be used in the data transfer. The CPU address to be used in the data transfer. The CPU treats this signal as one or more output ports.treats this signal as one or more output ports.•The DMA Count Register, also called Word Count The DMA Count Register, also called Word Count Register, contains the no. of bytes of data to be Register, contains the no. of bytes of data to be transferred. Like the DMA address register, it too is transferred. Like the DMA address register, it too is treated as an O/P port (with a diff. Address) by the treated as an O/P port (with a diff. Address) by the CPU.CPU.•The DMA Control Register accepts commands from The DMA Control Register accepts commands from the CPU. It is also treated as an O/P port by the CPU.the CPU. It is also treated as an O/P port by the CPU.contcontAlthough not shown in this fig., Although not shown in this fig., most DMA controllers also have a most DMA controllers also have a Status Register. This
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