Sequential LogicSequential Circuits4 Basic types of Flip-FlopsGated D-LatchD Flip-FlopJK – Flip FlopClocked JK – Flip FlopT Flip-FlopD and JK Flip-FlopHow to use JK to implement D Flip-FlopHow to use JK to implement T Flip-FlopHow to use D to implement JK Flip-FlopSlide 13How to use T to implement JK Flip-FlopSlide 15How to use D to implement T Flip-FlopSlide 17How to use T to implement D Flip-FlopSlide 19SR-Flip FlopSlide 21Clocked SR Flip-FlopInstabilityEdge and level-triggered Flip FlopPositive-edge-triggered D Flip-FlopReferencesSequential Logic •Combinatorial components: the output values are computed only from their present input values.•Sequential components: their output values are computed using both the present and past input values.•Sequential circuits can contain only a finite number of states finite state machines•Synchronous and AsynchronousSequential Circuits•Contains Memory Elements •Asynchronous sequential circuits change their state and output values when input changes•Synchronous sequential circuits change their output values at fixed points of time, which are specified by the rising or falling edge of a clock signal•Clock period is the time between successive transitions in the same direction•Active high – state changes occur at the clock’s rising edge( on higher voltage)•Active low – state changes occur at the clock’s falling edge( on lower voltage)4 Basic types of Flip-Flops•SR, JK, D, and T•JK ff has 2 inputs, J and K need to be asserted at the same time to change the state•D ff has 1 input D (DATA), which sets the ff when D = 1 and resets it when D = 0•T ff has1 input T (Toggle), which forces the ff to change states when T = 1•SR ff has 2 inputs, S (set) and R (reset) that set or reset the output Q when assertedGated D-Latch•Ensures S and R inputs never equal to 1 at the same time•Useful in control application where setting or resetting a flag to some condition is needed•Stores bits of information•Constructed from a gated SR latch and a Data latchD Flip-FlopCharacteristics :SynchronousAvoids the instability of RS flip-flopRetains its last input valueTo set the ff, place 1 on D input and pause the CK inputTo reset, place 1 on D input and pause the CK inputD Q+0101Q+ = Next StateJK – Flip FlopJ – SetK – ResetJ = K = 0 – output does not changeJ = K = 1 – invert the outputsClocked JK – Flip FlopT Flip-FlopT Q+01QQ’T = 1 force the state changeT = 0 state remain the sameD and JK Flip-FlopD Q+0101J K Q+0 00 11 01 1Q01Q’How to use JK to implement D Flip-FlopD Q+0101J K Q+0 00 11 01 1Q01Q’D ff’s property:When in = 0, the out(Q+) = 0.When in = 1, the out(Q+) is 1 invert K invert KDHow to use JK to implement T Flip-FlopT Q+01QQ’J K Q+0 00 11 01 1Q01Q’T ff’s property:When in = 0, the out(Q+) = no changeWhen in = 1, the out(Q+) is = complement No change State changeTHow to use D to implement JK Flip-FlopKQ 00 01 11 10 J 0 1 0(Q) 1(Q) 0 0 1 1 0(Q’) 1(Q’)J K Q+0 00 11 01 1Q01Q’D Q+0101 D = JQ’ + K’Q(Q ) = no state change(Q’) = state changeHow to use D to implement JK Flip-Flop D = JQ’ + K’QJKHow to use T to implement JK Flip-FlopKQ 00 01 11 10 J01 0 0 1 0 1 0 1 1 J K Q+0 00 11 01 1Q01Q’T Q+01QQ’T = KQ + JQ’How to use T to implement JK Flip-FlopT = KQ + JQ’How to use D to implement T Flip-FlopT Q+01QQ’Q+ 0 1T 0 1 0 1 1 0D = TQ’ + T’QD Q+0101How to use D to implement T Flip-FlopD = TQ’ + T’QTHow to use T to implement D Flip-FlopT Q+01QQ’D Q+0101T = DQ’ + D’QQ+ 0 1D01 0 1 1 0How to use T to implement D Flip-FlopT = DQ’ + D’QDSR-Flip Flop S R Q Q’0 01 00 11 1Q Q’1 00 1 0 0S R Q Q’1 10 11 00 0Q Q’1 00 1 1 1RESETSETSETRESETSR-Flip Flop •Asynchronous •If S=0 and R=1, Q is set to 1, and Q’ is reset to 0•IF R=0 and S=1, Q is reset to 0, and Q’ is set to 1•If S=1 and R=1, Q and Q’ maintain their previous state•If S=0 and R=0, a transition to S=1, R=1 will cause oscillationClocked SR Flip-FlopSimilar to SR Flip-flop but with extra control input C, which enables or disables the operation of S and R inputs.C=1 EnabledC=0 Disabled, circuit persists in preceding stateInstability•RS flip-flops can become unstable if both R and S are set to 0•All sequential elements are fundamentally unstable under certain conditions–Invalid transitions–Transitions too close together–Transitions at the wrong timeEdge and level-triggered Flip Flop•Digital circuit often form loops, flip-flops oscillations can •Oscillation will not occur because by the time an output change cause an input change, the activating edge of the CK signal will be gone•Positive edge triggered – ff responds to a positive going edge of clock•Negative edge triggered – responds to a negative-going edgePositive-edge-triggered D Flip-FlopWhen CLK=0 the master latch is open and the content of D is transferred to QMWhen CLK=1 the master is closed and its output is transferred to the slaveMaster and slave latches are never enabled at the same timeReferences•www.play-hookey.com/digital •www.infopad.eecs.berkeley.edu/~icdesign/SLIDES/slides6.pdf •www.cs.mun.ca/~paul/cs3724/material/web/notes/node14.html •Dos Reis, Assembly Language and Computer Architecture Using C++ and
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