Relationship between Address Width and Memory HeightSlide 2Memory Map for a small computer systemUsually memory RAMs and ROMs are not normally matched to the width of the address buss. What happens then? The remaining address buses will be fed to into a separate decoder that will connect to the Chip select (C/S) pins on the memory pack to complete the addressing.Sometimes the address is not fully decoded What happens then? Multiple images of memory packs within the same address. ( it is not a huge deal, it can still work )Some computers have their IO ports inserted into the main memory map. --> This will cause an inconvenient segmentation of the memory. And Decoding circuits will be a way more conplex because of the routine differences in access times between memory and port chipsIO Mapped scheme is the scheme where IO have different region in the address than the memory chips. Space occupied between the 2 is largely different: 4G compared to 64k To provide this scheme, the CPU needs to provide special instructions e.g. IN and OUT and more bus signals are needed.The Memory Sam Bouguerra CS 147 Fall 2008Relationship between Address Width and Memory Height16 MB1111 1111 1111 1111 11111 11110000 0000 0000 0000 0000 0000Memory height 2^24Memory WidthAddress Width = 24The Memory Sam Bouguerra CS 147 Fall 2008Extra Decoder Logic is needed to select the correct Memory Chip.If this is not done, all the Chips will respond to the every CPU call.Example phone area code.If 2 Chips respond simultaneously ---> System crash!When CPU sends out an address 0010 0001 1111 1010Upper part:The memory ChipLower part:The memory cell within the ChipThe Memory Sam Bouguerra CS 147 Fall 2008Memory Map for a small computer systemDevice Size Pins32 address bus Address RangePROM1RAM 1RAM 2RAM 31 Mbyte16 Mbyte16 Mbyte16 Mbyte202424240000 0000 xxxx ++++ ++++ ++++ ++++0000 0001 ++++ ++++ ++++ ++++ ++++0000 0010 ++++ ++++ ++++ ++++ ++++0000 0011 ++++ ++++ ++++ ++++ ++++0000 0000 – 000F FFFFF0100 0000 – 01FF FFFF0200 0000 – 02FF FFFF0300 0000 – 03FF FFFFDesigning computer memories to deliver the best possible accessTimes for users an maximum flexibility for administrators, when they Install extra modules, is complex and trickyThe Memory Sam Bouguerra CS 147 Fall 2008Usually memory RAMs and ROMs are not normally matched to the width of the address buss.What happens then?The remaining address buses will be fed to into a separate decoder that will connect to the Chip select (C/S) pins on the memory packto complete the addressing.The Memory Sam Bouguerra CS 147 Fall 2008Sometimes the address is not fully decodedWhat happens then?Multiple images of memory packs within the same address.( it is not a huge deal, it can still work )The Memory Sam Bouguerra CS 147 Fall 2008Some computers have their IO ports inserted into the main memory map.--> This will cause an inconvenient segmentation of the memory. And Decoding circuits will be a way more conplex because of the routine differences in access times between memory and port chipsCPUIO Dev 1IO Dev 2RAM 2RAM 1ROM80 0000-80 002FMemory Map00 0000-01 FFFFLots ofUnused spaceThe Memory Sam Bouguerra CS 147 Fall 2008IO Mapped scheme is the scheme where IO have different region in the address than the memory chips.Space occupied between the 2 is largely different: 4G compared to 64kTo provide this scheme, the CPU needs to provide special instructions e.g. IN and OUT and more bus signals are
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