Lecture 8 Sequential LogicImplement D Flip-flop by T Flip-flopPowerPoint PresentationSlide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Random-Access MemoryBinary CounterRegisterClocks and SequencersReal World ApplicationState DiagramsImportant Rule for State DiagramThe Alarm ClockState Diagram for The Alarm Clock (a)The alarm clock problem with inaction statesState Diagram for The Alarm Clock (b)State Tables for The JK Flip-FlopCondition in Terms of J and KMealy and Moore MachinesMoore MachinesSlide 43Mealy MachinesSlide 45Designing State DiagramsModulo 6 CounterState Table for The Modulo 6 CounterState Diagram for The Modulo 6 Counter (Mealy)State Diagram for The Modulo 6 Counter (Moore)String CheckerState Table For String CheckerState Diagrams for the String Checker ( Mealy)State Diagrams for the String Checker (Moore)Lecture 8 Sequential LogicProf. Sin-Min LeeDepartment of Computer ScienceImplement D Flip-flop by T Flip-flop0 10 01 10 10 11 0D TQQ0101T = D Q’ + D’ Q D D’TImplement JK Flip-flop by D Flip-flop0 10 10 01 01 1J KQ0 00 11 11 0D = J Q’ + K’ QD0 1J KQ0 00 11 11 00 10 01 01 1D Q+0101JKQQ’Implement JK Flip-flop by T Flip-flop0 10 10 01 01 1J KQ0 00 11 11 0T = J Q’ + K QT0 1J K0 00 11 11 00 00 11 11 0T Q+01QQ’JKQQ’QQ+J K Q+0 00 11 01 1Q01Q’Implement T Flip-flop by JK Flip-flop0 X1 XX 1X 0 J K 0 00 11 01 1TQ01 0 1 1 0 Q Q+0 1TQ01 0 X 1 X0 1TQ01 X 0 X 10 1J = TK = TRandom-Access Memory•Can read and write at any point in memory•Implemented using D Flip-Flops•Each row contains 16 Flip-Flops •A DecoderBinary Counter• Holds each pulse in memory•Each pulse add another number •Binary formatRegister•Used to hold one item of information•CPU’s have many registers •AX is an example in AssemblyClocks and Sequencers•To perform operations a CPU often requires a specific sequence of sub operations •A sequencer is used to make sure operations happen in correct order •A clock is a circuit that outputs 0’s and 1’s at specific frequenciesReal World Application•The RAM discussed is a model for a chip that can actually be found in a computer•The binary counter can be bought at http://www.web-tronics.com/webtronics/74hc161n.html for 45 cents each•The Flip-Flop circuits are models of usable chipsState DiagramsState Diagrams•A state diagram:–Each state is represented by a circled vertex–Each row of the state table is shown as directed arcJ’YImportant Rule for State Diagram•State diagram has same situation as state table. Their conditions should be mutually exclusive, no input values should meet the condition of more than one arc.The Alarm Clock The Alarm Clock Present stateAlarm Weekday Next stateTurn off alarmOn X Awake in bedYesAsleepAwake in bed Off YesAwake and upNoAwake in bedOffNoAsleep NoState Diagram for The Alarm Clock State Diagram for The Alarm Clock (a)(a)Awake in bedAsleepAlarm’AlarmAwake and up1 (Always)AlarmAlarm’ /\ Weekday’ Alarm’ /\ WeekdayTurn off Alarm = Yes( a )The alarm clock problem with The alarm clock problem with inactioninaction statesstatesPresent state Alarm Weekday Next state Turn off alarmAsleep Off XAsleepNoAsleepOnAwake in bedYesAwake in bedOnXAwake in bedyesAwake in bedOff Yes Awake and up NoAwake in bed Off No AsleepNoAwake and up XXAwake and up NoXState Diagram for The Alarm ClockState Diagram for The Alarm Clock (b)( b )Asleep Awake in bedAwake and upAlarm’ / 0Alarm / 1Alarm’ /\ Weekday’ / 01 (Always) / 0Alarm’ /\ Weekday / 0Alarm / 11 = yes turn off alarm (output)0 – no turn off alarm (output)State Tables for The JK Flip-FlopState Tables for The JK Flip-Flop( a )Present StateYZZZZYYYJ K0011001101010101Next State QYYZZZYZY00111010Condition in Terms of J and KCondition in Terms of J and KZJKJ’ K’Q=0Q=1YMealy and Moore MachinesMealy and Moore Machines•A finite state machine can represent outputs in one of two ways–Moore Machines–Mealy MachinesMoore MachinesMoore Machines–Moore Machines•Associates its outputs with the states.•Output values depend only on the state and not on the transitions.•It requires less hardware to produce the output values•It is well suited for representing the control units of microprocessors and cpu.State Diagram for The Alarm Clock State Diagram for The Alarm Clock (a)(a)Awake in bedAsleepAlarm’AlarmAwake and up1 (Always)AlarmAlarm’ /\ Weekday’ Alarm’ /\ WeekdayTurn off Alarm = YesMoore MachineMealy MachinesMealy Machines–Mealy Machines•Associates outputs with the transitions.•It depends on both its state and its input valuesState Diagram for The Alarm ClockState Diagram for The Alarm Clock (b)Mealy MachineAsleep Awake in bedAwake and upAlarm’ / 0Alarm / 1Alarm’ /\ Weekday’ / 01 (Always) / 0Alarm’ /\ Weekday / 0Alarm / 1Designing State DiagramsDesigning State Diagrams•Counter•String Checker•Toll BoothModulo 6 CounterModulo 6 Counter•A modulo 6 counter is a 3-bit counter that counts through the sequence.–000 001 010 011 100 101 000…–0 1 2 3 4 5 0 …Unlike a regular 3-bit counter110(6) and 111(7) do not count0 0 00010 1 00 1 11 0 01 0 11 1 01 1 1State Table for The Modulo 6 CounterState Table for The Modulo 6 CounterPresent State Next State C V2 V1 V0US0S0S1S1S2S2S3S3S4S4S5S5100101010101S0S1S1S2S2S3S3S4S4S5S5S01000000000010 0 00 0 10 0 10 1 00 1 00 1 10 1 11 0 01 0 11 0 10 0 01 0 0State Diagram for The Modulo 6 State Diagram for The Modulo 6 Counter (Mealy)Counter (Mealy)S0S5S1S4S2S30 / 1000 0 / 0001 0 / 00101 / 0001 1 / 00101 / 00110 / 00111 / 01000 / 01001 / 01010 / 01011 / 1000( a ) MealyState Diagram for The Modulo 6 State Diagram for The Modulo 6 Counter (Moore)Counter (Moore)S5S0 S1S4S2S3U’U’U’U’U’U’C=1V =000UC=0 V=0010UC=0V=010UC=0V=011UC=0V=100UC=0V=101( b ) MooreString CheckerString Checker•A String Checker inputs a string of• bits, one bits per clock cycle.•It
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