Mid3 RevisionSlide 2Figure 9--1 A 2-bit asynchronous binary counter.Figure 9--2 Timing diagram for the counter of Figure 9-1, output waveforms are shown in green.Slide 5Slide 6Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle.Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.Figure 9--5 Four-bit asynchronous binary counter and its timing diagram.Figure 9--11 A 2-bit synchronous binary counter.Figure 9--12 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).Figure 9--13 Timing diagram for the counter of Figure 9-11.Figure 9--14 A 3-bit synchronous binary counter.Figure 9--15 Timing diagram for the counter of Figure 9-14.Slide 15Figure 9--27 General clocked sequential circuit.Figure 9--28 State diagram for a 3-bit Gray code counter.Slide 18Slide 19Figure 9--29 Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8.Figure 9--30 Karnaugh maps for present-state J and K inputs.Figure 9--31 Three-bit Gray code counter.Figure 9—32 : Example 9-5Slide 24Slide 25Figure 9--33Figure 9--34Figure 9--35 Example 9-6 - State diagram for a 3-bit up/down Gray code counter.Slide 29Slide 30Figure 9--36 J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable.Figure 9--37 Three-bit up/down Gray code counter.Figure 9--54 Functional block diagram for parking garage control.Figure 9--55 Logic diagram for modulus-100 up/down counter for automobile parking control.Figure 9--56 Parallel-to-serial data conversion logic.Figure 9--57 Example of parallel-to-serial conversion timing for the circuit in Figure 9-56.Figure 9--66 Traffic light control system block diagram and light sequence.Figure 9--67 Block diagram of the sequential logic.Figure 9--68 State diagram showing the 2-bit Gray code sequence.Figure 9--69 Sequential logic.Slide 41Slide 42Slide 43Figure 9--70Figure 9--71Figure 9--72Slide 47MultiplexerDecoderSlide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56Slide 57Slide 58Slide 59Slide 60Slide 61Slide 62Mid3 RevisionProf. Sin-Min Lee2Counters3Figure 9--1 A 2-bit asynchronous binary counter. Asynchronous Counter Operation4Figure 9--2 Timing diagram for the counter of Figure 9-1, output waveforms are shown in green.567Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle.8Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.9Figure 9--5 Four-bit asynchronous binary counter and its timing diagram.10Figure 9--11 A 2-bit synchronous binary counter.Synchronous Counter Operation11Figure 9--12 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).12Figure 9--13 Timing diagram for the counter of Figure 9-11.13Figure 9--14 A 3-bit synchronous binary counter.14Figure 9--15 Timing diagram for the counter of Figure 9-14.1516Figure 9--27 General clocked sequential circuit.Design of Synchronous Counters17Figure 9--28 State diagram for a 3-bit Gray code counter.Step 1: State Diagram18Step 2: Next-State Table19Step 3: Flip-Flop Transition Table20Figure 9--29 Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8.Step 4: Karnaugh Maps21Figure 9--30 Karnaugh maps for present-state J and K inputs.Step 5: Logic Expressions for Flip-Flop Inputs22Figure 9--31 Three-bit Gray code counter. Step 6: Counter Implementation23Figure 9—32 : Example 9-5242526Figure 9--3327Figure 9--3428Figure 9--35 Example 9-6 - State diagram for a 3-bit up/down Gray code counter.293031Figure 9--36 J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable.32Figure 9--37 Three-bit up/down Gray code counter.33Figure 9--54 Functional block diagram for parking garage control.Counter Applications : Automobile Parking Control34Figure 9--55 Logic diagram for modulus-100 up/down counter for automobile parking control.35Figure 9--56 Parallel-to-serial data conversion logic.Counter Applications : Parallel-to-Serial Data Conversion (Multiplexing)36Figure 9--57 Example of parallel-to-serial conversion timing for the circuit in Figure 9-56.37Figure 9--66 Traffic light control system block diagram and light sequence.Application38Figure 9--67 Block diagram of the sequential logic.39Figure 9--68 State diagram showing the 2-bit Gray code sequence.40Figure 9--69 Sequential logic.41424344Figure 9--7045Figure 9--7146Figure 9--72•You have invented a new type of flip-flop that you have called MY flip-flop. The two inputs are M and Y, the outputs are Q and Q'. The truth table of your flip-flop is given below. •Show how to implement a SR flip-flop using the new MY flip-flopMultiplexer•Given the following implementation using a 4:1 multiplexer, what is the function L(A,B,C,D)?•A. m(0, 1, 2, 3)•B. m(5, 6, 8, 11)•C. m(1, 2, 5, 6)•D. m(1, 2, 5, 6, 9, 10, 13, 14)•E. m(2, 5, 9, 14)C
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