RISC and PipeliningThe Basis for RISCRISC characteristicsPowerPoint PresentationSlide 5Slide 6Slide 7Slide 8Instructions PipelinesInstruction Pipelines ConflictsData ConflictsSolution for the Data ConflictsBranch ConflictsSolution for the Branch ConflictsRISC vs. CISCSlide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 3311.3.1 Instruction PipelineSlide 35An instruction pipeline processes an instruction the way the assembly line processes a product.Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56Slide 57Slide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68Slide 69Slide 70Slide 71Slide 72Slide 73Slide 74Slide 75Slide 76The MIPS processor uses a five-stage pipeline; it decodes the instruction and selects the operand registers in separate stages. These three configurations are shown in the following figure.Slide 78Slide 79A Single Pipelined Control Unit Offers Several Advantage:RISC and PipeliningProf. Sin-Min LeeDepartment of Computer ScienceThe Basis for RISC•Use of simple instructions•One of their key realizations was that a sequence of simple instructions produces the same results as a sequence of complex instructions, but can be implemented with a simpler (and faster) hardware design. Reduced Instruction Set Computers---RISC machines---were the result.RISC characteristics•Simple instruction set. •In a RISC machine, the instruction set contains simple, basic instructions, from which more complex instructions can be composed. •Same length instructions.•Each instruction is the same length, so that it may be fetched in a single operation. •1 machine-cycle instructions. • Most instructions complete in one machine cycle, which allows the processor to handle several instructions at the same time. This pipelining is a key technique used to speed up RISC machines.Instructions Pipelines•It is to prepare the next instruction while the current instruction is still executing. •A Three states RISC pipelines is :1. Fetch instruction 2. Decode and select registers 3. Execute the instructionClockStage1 2 3 4 5 6 71 i1 i2 i3 i4 i5 i6 i72 - i1 i2 i3 i4 i5 i63 - - i1 i2 i3 i4 i5Instruction Pipelines Conflicts•It divided into two categories.–Data Conflicts–Branch Conflicts•When the current instruction changes a register that the next one needed, data conflicts happens.•When the current instruction make a jump, branch conflicts happens.Data Conflicts•To show this conflicts, consider the following code 1. R1 <- R2 + R32. R4 <- R1 + R33. R5 <- R1 + R3•The first instruction change the register that the second needed. However, the second instruction have already fetch the values in R1 and R3. Therefore, incorrect result will be returned.Solution for the Data ConflictsCompiler Level•Solve by No-op–We can add No-op statements between 1 and 2•Instruction reordering–Reordering it so 3 is fetch before 2Hardware Level•Stall insertion–Same as No-op but Stall are inserted by the hardware•Data forwarding–Calculated result are forwarded to stage2Branch Conflicts•Consider the code:1. R1 <- R2 + R32. R4 <- R5 + R63. JUMP 104. R7 <- R8 +R9..10. R13 <- R14 + R15•The codes 4 and 5 have been fetched before the jump made so illegal changes may made.Solution for the Branch ConflictsCompiler Level•Solve by No-op–We can add No-op statements between 2 and 3•Instruction reordering–Reordering it so 3 is fetch first and then do 1 and 2Hardware Level•Annulling–Do the instruction but don’t save any changes•Branch prediction–Predict the result and fetch the assumed code. If the prediction are true, then save changes or annuls itRISC vs. CISC•RISC have fewer and simpler instructions, therefore, they are less complex and easier to design. Also, it allow higher clock speed than CISC. However, When we compiled high-level language. RISC CPU need more instructions than CISC CPU.•CISC are complex but it doesn’t necessarily increase the cost. CISC processors are backward compactable.Why RISC is betterThe 80/20 rule: Analysis of the instruction mix generated by CISC compilers, shows that more than 80% of the instructions generated and executed used only 20% of an instruction set. It wasan obvious conclusion that if this 20% of instruction was speeded up, the performance benefits would be far greater. Further analysis shows that these instructions tend to perform the simpler operationsand use only the simpler addressing modes. For the CISC machine, all the effort invested in processor design to provide complex instructions and thereby reduce the compiler workload was being wasted. .•Less cost: Since only the simpler instructions are needed, the processor hardware required to implement them could be reduced in complexity. Therefor it should be possible to design a more performance processor with less cost. •Good performance: With a simpler instruction set, it should possible for a processor to execute its instruction in a single clock cycle. Higher performance can be achieved.Pipelining: A key RISC techniqueRISC designers are concerned primarily with creating the fastest chip possible, and so they use a number of techniques, including pipelining. Pipelining is a design technique where the computer's hardware processes more than one instruction at a time, and doesn't wait for one instruction to complete before starting the next.The advantages of RISCImplementing a processor with a simplified instruction set design provides several advantages over implementing a comparable CISC design: (1) Speed. Since a simplified instruction set allows for a pipelined, superscalar design RISC processors often achieve 2 to 4 times the performance of CISC processors using comparable semiconductor technology and the same clock rates. (2) Simpler hardware. Because the instruction set of a RISC processor is so simple, it uses up much less chip space; extra functions, such as memory management units or floating point arithmetic units, can also be placed on the same chip. Smaller chips allow a semconductor manufacturer to place more parts on a single silicon wafer, which can lower the per-chip cost dramatically. (3) Shorter design cycle. Since RISC processors are simpler than corresponding CISC processors, they can be designed more
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