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SJSU CS 147 - Computer Buses

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Computer BusesContentsConceptsConcepts (cont.)Slide 5Slide 6MeasurementSlide 8Synchronous Bus vs. Asynchronouse BusSlide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Bridge-based bus architecturesSlide 21Slide 22Slide 23Internal Communication MethodologiesProgrammed I/O (polling)Slide 26Interrupt-Drive I/O (PIO)Direct Memory Access (DMA)Slide 29Slide 30ReferencesComputer BusesSJSU - Fall 2008CS 147Vu LuuContents1. Concepts2. Measurement3. OperationConcepts•A bus is a collection of wires and connectors through which the data is transmitted.•Bus = address bus + data bus–Data bus: transfers actual data.–Address bus: transfers information about data and where it should go.Concepts (cont.)•Bus protocol: rules determining the format and transmission of data through bus.•Parallel bus: data is transmitted in parallel.–Advantage: fast–Disadvantage: high cost for long distance transmission, interference between lines at high frequency.•Serial bus: data is transmitted in serial.–Advantage: low cost for long distance transmission, no interference.–Disadvantage: slow•Bus master: The device controls bus. Other devices are slaves.Concepts (cont.)•Local (system) bus: CPU  main memory.•Front side bus:–Original concept: CPU  components–Modern Intel architecture: CPU  NorthBridge chipset•Back side bus: CPU  L2 cache•Memory bus: Northbridge chipset  main memory•AGP bus: Northbridge chipset  GPU•ISA, EISA, VLB, PCI, Firewire, USB, PCI-Express bus: motherboard  peripheral devices.Measurement•Bus width: indicates the number of wires in the bus for transferring data.•Bus bandwidth: refers to the total amount of data that can theoretically be transferred on the bus in a given unit of time.Bus Width (bit) Bandwidth (MB/s)16-bit ISA 16 15.9EISA 32 31.8VLB 32 127.2PCI 32 127.264-bit PCI 2.1 (66 MHz) 64 508.6AGP 8x 32 2,133USB 2 1 Slow-Speed: 1.5 Mbit/sFull-Speed: 12 Mbit/sHi-Speed: 480 Mbit/sFirewire 400 1 400 Mbit/sPCI-Express 16x version 2 16 8,000Width and Bandwidth of Some Typical BusesSynchronous Bus vs. Asynchronouse Bus•A bus can be classified as one of two type: synchronous and asynchronous.•Synchronous bus: there is a common clock that synchronizes bus operations.•Asynchronous bus: there is no common clock. Bus master and slaves have to “handshake” during transmission process.1. CPU places address of the location it wants to read on the address lines.12. After the voltages on the address lines have become stable, CPU asserts MREQ and RD lines.123. Memory controller locates memory location and loads it into data lines.1234. CPU takes data from data lines and then de-asserts MREQ and RD to release the bus.12341. CPU puts address on the bus.12. CPU asserts MREQ and RD lines.123. CPU asserts MSYN line. Memory controller locates and loads data from memory to data lines.1234. Memory controller locates, loads data from memory to data lines, and asserts SSYN line.123445. CPU takes data from data lines and then de-asserts MREQ, RD, and MSYN. 123445556. Finally, memory controller de-assert SSYN. 123445556Bridge-based bus architectures•System includes a lot of buses which are segregated by bridges.•Advantage: buses can simultaneously operate.•Intel architecture:Bridging with AMD processorsBridging with VIA C7 processorsInternal Communication Methodologies•Programmed I/O (polling)•Interrupt-drive I/O•Direct Memory Access (DMA)Programmed I/O (polling)•CPU polls each device to see if it needs servicing.•Drawback: The CPU wastes time for polling devices (busy-wait.)Mode Maximum transfer rate (MB/s)mode 0 3.3mode 1 5.2mode 2 8.3mode 3 11.1mode 4 16.7mode 5 20mode 6 25Programmed I/O modes in the ATA interfaceInterrupt-Drive I/O (PIO)•Device requests service through a special interrupt request line that goes directly to the CPU.•No busy-wait. More efficient than PIO.Direct Memory Access (DMA) •Devices transfer data directly to and from memory bypasses the CPU.•Very efficient mode. CPU is free to do other operations.Modes Maximum transfer rate (MB/s)Multi-word DMA 1 13.3Multi-word DMA 2 16.6Ultra DMA 0 16.7Ultra DMA 1 25.0Ultra DMA 2 33.3Ultra DMA 3 44.4Ultra DMA 4 66.7Ultra DMA 5 100Ultra DMA 6 133DMA modes in the ATA interfaceReferences•Murdocca, Miles and Heuring, Vincent. Computer Architecture and Organization: An Integrated Approach. John Wiley & Sons, Inc., 2007. p.303 – p.316.•Kozierok, Charles. The PC Guide.


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SJSU CS 147 - Computer Buses

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