CISC…AGAIN!!! (and a bit o’ RISC, too)AgendaCISC’s RootsDepartment of Redundancy DepartmentExempli Gratia = E.G. != I.E.A-1 Computer InstructionsPre-CISC exampleThree possible problemsHow does CISC solve this problem?Post-CISC exampleResultDrawbacksHere comes the 80’s and a….Birth of RISC & CISC???Slide 15Slide 16Are you ready to rumble?Warning, Geeky Conspiracy Theory AheadCISC + Pipelining = i486RISC’s people: “What we meant…”Slide 2110 YearsSlide 23Hilarious!!In Conclusion…Thank you!SourcesCISC…AGAIN!!! (and a bit o’ RISC, too)by Javier ArboledaAgendaBrief HistoryAn example of “Closing the semantic gap”Drawbacks of CISCInteresting RISC vs. CISC stuffCISC’s RootsBack in the 70’s memory & software = $$$Hardware… not so much $Move burden of code from software & memory to hardware“Closing the semantic gap”Department of Redundancy DepartmentSo, to reiterate, CISC architecture type was created to :Reduce software developing costs by making compilers easier to write and code easier to debugReduce calls to memory, thus making it possible to do more with less memory which at the time was the most expensive part of a computer systemExempli Gratia = E.G. != I.E.Let’s pretend that…H is the name for a high-level language. This language has a function Cube() which will cube an integerH compiler translates code into assembly language for the A-1 computer, which only has two instructionsA-1 Computer InstructionsMove [destination register, integer or source register]This instruction takes a value, either an integer or the contents of another register, and places it in the destination register. So Move [D, 5] would place the number 5 in register D. Move [D, E] would take whatever number is stored in E and place it in D Mult [destination register, integer or source register]This instruction takes the contents of the destination register and multiplies it by either an integer or the contents of the source register, and places the result in the destination register. So Mult [D, 70] would multiply the contents of D by 70 and place the results in D. Mult [D, E] would multiply the contents of D by the contents of E, and place the result in DPre-CISC exampleStatements in H Statements in Assembly for A-1 computer1. A = 20;2. B = Cube(A);1. Move [A, 20]2. Mult [A, A]3. Mult [A, A]4. Move [B, A]Here it takes four statements in the A-1 assembly to do the work of two statements in H since the A-1 computer has no instruction for taking the Cube of a numberThree possible problems1. If the program H uses Cube() many times, then assembly code will be relatively larger, which is bad for the A-1 computer that has very little memory2. With computer speeds being so slow, compiler takes a long time to translate all of the Cube() statements to multiple Mult[] instructions3. Programming in assembly language would be time consuming, tedious, and difficult to debugHow does CISC solve this problem?Include a Cube instruction in the instruction set of the next generation of computers, A-2Cube[destination register, source register] This instruction takes the contents of the source register and cubes it. It then places the result in the destination register. So Cube [D, E] takes whatever value is in E, cubes it, and places the result in DPost-CISC exampleStatements in H Statements in Assembly for A-2 computer1. A = 20;2. B = Cube(A);1. Move [A, 20]2. Cube[B, A]One-to-one correspondence between H and assembly code“Semantic gap” is closedComplexity has moved from the software level to the hardware levelResultCompiler does less work to translateLess memory neededEasier to debugDrawbacksWhen using an instructions set with so many instructions, the decode function of the computer system must be able to recognize a wide variety of functions. As a result, the decode logic, while time critical for purposes of performance, grows to be quite complexNot every one of the complex instructions are used for each software program, and thus much of the decode logic functionality is seldom used during operationAnother problem arises from the fact that the complex instructions are often of different lengths, i.e., each instruction could consist of any number of operands and takes any number of cycles to executeHere comes the 80’s and a….Birth of RISC & CISC???RISC = Reduced instruction set computerPrevious to RISC, CISC was not called “CISC,” it was just the “really good way to do things computer” or RGWTDTC (just kidding)The term “complex instruction set computer” was forced upon anything else that was not RISCBloody hell, it’s obvious that RISC and pointy hats are the future, mate!!!Pipelining… BRILLIANT!!RISC = GOOD!!!!CISC = BAD!!!RISC > CISCAre you ready to rumble?RISCCISCVSWarning, Geeky Conspiracy Theory AheadCISC + Pipelining = i486CISC chips started using pipelining with the Intel i486 processor. Now what, RISC?!?Several years later Apple starts using the G3 (third generation PowerPC processors)This was a RISC chip which actually had more instructions than Intel’s Pentium II CISC processor!Hold up, Isn’t RISC suppose to have a reduced number of instructions? Isn’t that why RISC is so much better than CISC?RISC’s people: “What we meant…”Proponents of RISC started to claim that the actual number of instructions was never intended to be reduced; rather, only the individual instructions themselves were to be reduced in cycle time and complexityAll the hoopla was speculated to have been generated from Apple’s camp and users who must insist that the processors in their Macs are pure RISC chips, sinceRISC = GOOD!!!!CISC = BAD!!!RISC > CISC10 YearsThe argument about RISC being so much better than CISC starts to quiet down, and why?What announcement did Apple make in 2005?No more PowerPC for Apple,Now it’s all about Intel!Brilliant!!Hilarious!!In Conclusion…CISC chips dominate the personal computer marketLine between RISC and CISC continues to blurThe RISC > CISC || CISC > RISC debate is unheard ofThank
View Full Document
Unlocking...