SPARC ArchitectureOutlineRISC: Defintion & BackgroundRISC: Which instructions are used most?RISC: Design PrinciplesRISC: Design Principles (cont)RISC: AdvantagesRISC: Advantages (cont)RISC: DisadvantagesRISC: Solutions & Impure RISCRISC: Register-windowSPARC: What is it?SPARC: Brief HistorySPARC: Brief History (cont)SPARC: Architecture FeaturesSPARC: Integer & Floating-point UnitsSPARC: Core PipelineSPARC: Multiprocessor instructionsSPARC: Firsts...SPARC in the MarketplaceTODAY: ArchitectureTODAY: Current FeaturesTOMORROW: Future of SPARCReferencesSPARC Architecture▬▀►By Trevor TonnCS147 Spring 2009OutlineI. RISCII. The SPARC ArchitectureIII. SPARC in the MarketplaceIV. SPARC Today and TomorrowRISC: Defintion & Background•Reduced Instruction Set Computing, also called “load-store architecture” (due to the load-store instructions for accessing memory).•In the 1970's researchers noticed that a promising alternative to providing a large set of instructions to the ISA (instruction set arch.) would be to support only the most frequently used instructions, leaving the scarcely used instructions to be implemented by these as instruction sequences.RISC: Which instructions are used most?InstructionAverage (% of total execution)load 22Conditional branch 20Compare 16store 12add 8and 6sub 5Move register-register4call 1return 1Total 95Developers at IBM in the 70's found that 80% of a typical programs compu-tations required only about 20% of the instructions available in the processor's ISA.Focus: few, well-chosen, simple instructions and an optimizing compiler.RISC: Design Principles•Simple instructions and few addressing modes–Extra stuff left out saves space for other things•Instructions conform to a simple format–Reduces decoding delays•Load-store design–Everything operates on registers only; load from memory to the large number of registers first, then manipulate the registers only; store to memory when done.RISC: Design Principles (cont)•Hardwired control—no microcode–No translation from machine instructions, freeing CPU cycles needed to perform an instruction.–Also frees up chip space.•Goal: Execute one instruction per clock cycle–Uses pipelining and other features/principles described to get there.•Simplicity to facilitate the use of higher frequency clock cyclesRISC: Advantages•The fewer number of instructions required relatively little on-chip control logic, leaving space on the chip for other functions: enhances performance & versatility of the processor.–One example is the use of a large Register File (array of registers defined by the ISA) to allow for the register-window approach utilized in SPARC; lots of registers available. •Fast cycle time coupled with a high performance memory hierarchy can yield incredible processing power.RISC: Advantages (cont)The execution time for a large, compute-bound program can be expressed as the product of three terms:where:Ip = # of instr executed by programCp = avg # of cpu clock cycles per instr executed by programT = time per cycle (usually 1/clockCycle)MIPSp = million instr per secondThe second equation is a simplified version of the first. RISC's achieve high levelsof performance by minimizing Ip and maximizing MIPSp.How:Ip – lots of registers (> 16)Cp – simple instructionsT – 1 instr per cycle goalRISC: Disadvantages•Lack the more powerful instructions of CISC; requires many clock cycles to execute the many simple instructions that make up the equivalent instruction sequences.•Execution of a lot of small instructions causes a lot of instruction traffic—more than CISC.The advantages of a high clock frequency are at least partially offset by these characteristics.RISC: Solutions & Impure RISC•Instead of focusing on the most commonly used ops, add in some sets of complex instructions whose equivalent instruction sequences bring RISC to its knees.–If you need fast floating point performance, add in some complex fp instructions, for example.•Use free chip space to facilitate techniques to ease instruction traffic problem.–Register-window technique used in SPARC.These & other solutions go against some of the original design principles—impure RISC. Most implementations start with pure RISC and enhance it to fulfill requirements.RISC: Register-window•Each assembly procedure has a “window” of registers available to it, with an area of overlap between the procedure and the calling procedure to facilitate efficient parameter passing—no need to save or reload registers. •The windows change dynamically on procedure entry/exit.•Reduces instruction traffic.SPARC: What is it?•Scalable Processor ARChitecture•Designed by Sun Microsystems 1984-1987.•Based on RISC work done at UC Berkeley in 1980-82.•An architecture with many families of processors created by several companies.SPARC: Brief History3 major revisions to the architecture1) SPARC-V7, 32bit, 19862) SPARC-V8, 32bit, 19903) SPARC-V9, 64bit, 1993•UltraSPARC extension, 1995•Backwards, binary compatibility between all revisionsSPARC: Brief History (cont)V9 greatly improves upon V8:•64bit integer mul & div instructions•load/store floating-point quadword instructions–Load & store 128bits at a time•Software-settable branch prediction•Branch on register value–Reduces total number of instructions to execute•Conditional move instruction–Allows you to remove branch instructions.•Improved support for very large-scale multiprocessors–Relaxed memory ordering modelSPARC: Architecture Features•Integer unit (IU), floating-point unit (FPU), optional implementation-defined coprocessor (CP), each with its own set of registers.–Allows for maximum concurrency between integer, floating-point & coprocessor instructions.•All IU & FPU registers are 32bits wide•Instructions operate on single, pairs and quads of registers.SPARC: Integer & Floating-point Units•IU may contain between 40 and 520 general purpose registers. FPU has 32 registers.•Groups of 2 to 32 overlapping register windows–Register windows perform well with LISP and OO languages like Smalltalk. •No direct path between FPU & IU—must be accessed by load/store calls.•FPU can have several multipliers & adders–Implementation dependent•FPU: Concurrent execution of add/mul & load/storeSPARC: Core PipelineSPARC: Multiprocessor instructionsTwo special instructions support tightly coupled multiprocessors:•swap–Exchanges contents of
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