Cache Memory PerformanceComponents of PerformanceAverage Memory Access TimeAverage Memory Access Time versus Hit RatiosMapping StrategiesAssociative cache (FIFO)Direct Mapped CacheTwo-way set-associative cache (LRU)Two-bytesAssociative cache with a line size of 2 bytes (FIFO)Direct Mapped Cache with a line size of 2 bytesTwo-way set-associative cache with a line size of 2 bytesResourcesCache Memory PerformanceBrian ChanComponents of Performance•Cache Hits: requested data is in the cache.•Cache Misses: requested data is not in cache but is located in main memory.•Hit Ratio: ___hits____hits + missesAverage Memory Access Time•T = xc + y(c + m) = xc + yc + ym = (x + y)c + ym•T/(x + y) = c + ( y/(x + y) )m•Average access time = c + ((x + y – x)/(x + y))m= c + (1 – x/(x + y))m= c + (1 – h)mAverage Memory Access Time versus Hit RatiosMapping Strategies•Associative Cache•Direct-Mapped Cache•Two-way set-associative cacheAssociative cache (FIFO)Data A B C A D B E F A C D B G C H I A BA A A A A A A A A A A A A A A I I IB B B B B B B B B B B B B B B A AC C C C C C C C C C C C C C C C BA D D D D D D D D D D D D D DC E E E E E E E E E E E EH F F F F F F F F F F FE G G G G G GH H H HHit ? X X X X X X XDirect Mapped CacheDataA0B0C2A0D1B0E4F5A0C2D1B0G3C2H7I6A0B00 A B B A A B B B A A A B B B B B A B1 D D D D D D D D D D D D D DC 2 C C C C C C C C C C C C C C C CA 3 G G G G G GC 4 E E E E E E E E E E E EH 5 F F F F F F F F F F FE 6 I I I7 H H H HHit ? X X XTwo-way set-associative cache (LRU)DataA0B0C2A0D1B0E4F5A0C2D1B0G3C2H7I6A0B00A0 A1B0A1B0A0B1A0B1A1B0E0B1E0B1E1A0E1A0E1A0B0A1B0A1B0A1B0A1B0A1B1A0B0A10C 1D0 D0 D0 D1F0D1F0D1F0D0F1D0F1D0F1D0F1D0F1D0F1D0F1D0F1A 1C 2C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C1I0C1I0C1I0H 2 E 3G0 G0 G1H0G1H0G1H0G1H03Hit ? X X X X X X XTwo-bytes•Data pairs A J, B D, C G, E F, and I H.•Slightly slower since twice as much data is being loaded.Associative cache with a line size of 2 bytes (FIFO)Data A B C A D B E F A C D B G C H I A BA A A A A A A A A A A A A A I I I IJ J J J J J J J J J J J J J H H H HC B B B B B B B B B B B B B B B A AA D D D D D D D D D D D D D D D J JC C C C C C C C C C C C C C C C BH G G G G G G G G G G G G G G G DE E E E E E E E E E E E EF F F F F F F F F F F FHit ? X X X X X X X X X X XDirect Mapped Cache with a line size of 2 bytesDataA0B0C2A0D1B0E4F5A0C2D1B0G3C2H7I6A0B00 A B B A B B B B A A B B B B B B A B1 J D D J D D D D J J D D D D D D J DC 2 C C C C C C C C C C C C C C C CA 3 G G G G G G G G G G G G G G G GC 4 E E E E E E E E E E E EH 5 F F F F F F F F F F F FE 6 I I I I7 H H H HHit ? X X X X X X X XTwo-way set-associative cache with a line size of 2 bytesDataA0B0C2A0D1B0E4F5A0C2D1B0G3C2H7I6A0B00A0J0A1J1A1J1A0J0A1J1A1J1E0F0E0F0E1F1E1F1B0D0B0D0B0D0B0D0B0D0B0D0B1D1B0D01C 0B0D0B0D0B1D1B0D0B0D0B1D1B1D1A0J0A0J0A1J1A1J1A1J1A1J1A1J1A1J1A0J0A1J1A 1C 2C0G0C0G0C0G0C0G0C0G0C0G0C0G0C0G0C0G0C0G0C0G0C0G0C1G1C1G1C1G1C1G1H 3E 2I0H0I0H0I0H0I0H03Hit ? X X X X X X X X X X XResources•Carpielli, John D: Computer Systems Organization & Architecture (9.2.7)•Professor Lee’s Lecture on Oct. 21,
View Full Document
Unlocking...