Revision Midterm 3, RISC ArchitectureMemory HierarchySlide 3Slide 4Slide 5FIFOSlide 7Example of FIFO InconsistencyLRUSlide 10Example of LRU ConsistencyThe Basis for RISCAddressing modesInstruction PipelinePipeline StagesSlide 16Slide 17Slide 18Slide 19RISC characteristicsSlide 21Instructions PipelinesRISC vs. CISCSlide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45An instruction pipeline processes an instruction the way the assembly line processes a product.Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56The MIPS processor uses a five-stage pipeline; it decodes the instruction and selects the operand registers in separate stages. These three configurations are shown in the following figure.Slide 58Slide 59A Single Pipelined Control Unit Offers Several Advantage:Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68RISC AdvantagesCISC AdvantagesSlide 71Final Exam ProblemA Reduced Instruction Set Computer (RISC) architecture differs from a Complex Instruction Set Computer (CISC) architecture mainly in relation toRevision Midterm 3, RISC ArchitectureProf. Sin-Min LeeDepartment of Computer ScienceSan Jose State UniversityMemory HierarchyFIFO•When a page fault occurs, replace the one that was brought in first.201 2 3 4 1 2 5 1 2 5 3 4 5 Faults are shown in boxes; hits are not shown.9 page faults occurFIFO•Simplest page replacement algorithm.•Problem: can exhibit inconsistent behavior known as Belady’s anomaly.–Number of faults can increase if job is given more physical memory–i.e., not predictable21Example of FIFO Inconsistency•Same reference string as before only with 4 frames instead of 3.1 2 3 4 1 2 5 1 2 5 3 4 5 Faults are shown in boxes; hits are not shown.10 page faults occur22LRU23•Replace the page which has not been used for the longest period of time.1 2 3 4 1 2 5 1 2 5 3 4 5152215521 Faults are shown in boxes; hits only rearrange stack9 page faults occurLRU•More expensive to implement than FIFO, but it is more consistent.•Does not exhibit Belady’s anomaly•More overhead needed since stack must be updated on each access.24Example of LRU Consistency1 2 3 4 1 2 5 1 2 5 3 4 514322143152421545214•Same reference string as before only with 4 frames instead of 3. Faults are shown in boxes; hits only rearrange stack7 page faults occur25The Basis for RISC•Use of simple instructions•One of their key realizations was that a sequence of simple instructions produces the same results as a sequence of complex instructions, but can be implemented with a simpler (and faster) hardware design. Reduced Instruction Set Computers---RISC machines---were the result.Addressing modes•Limited number of addressing modes•The effective address is computed in a single clock cycle.Instruction Pipeline•Similar to a manufacturing assembly line1. Fetch an instruction2. Decode the instruction3. Execute the instruction4. Store results•Each stage processes simultaneously (after initial latency)•Execute one instruction per clock cyclePipeline Stages•Some processors use 3, 4, or 5 stagesRISC characteristics•Simple instruction set. •In a RISC machine, the instruction set contains simple, basic instructions, from which more complex instructions can be composed. •Same length instructions.RISC characteristics•Each instruction is the same length, so that it may be fetched in a single operation. •1 machine-cycle instructions. • Most instructions complete in one machine cycle, which allows the processor to handle several instructions at the same time. This pipelining is a key technique used to speed up RISC machines.Instructions Pipelines•It is to prepare the next instruction while the current instruction is still executing. •A Three states RISC pipelines is :1. Fetch instruction 2. Decode and select registers 3. Execute the instructionClockStage1 2 3 4 5 6 71 i1 i2 i3 i4 i5 i6 i72 - i1 i2 i3 i4 i5 i63 - - i1 i2 i3 i4 i5RISC vs. CISC•RISC have fewer and simpler instructions, therefore, they are less complex and easier to design. Also, it allow higher clock speed than CISC. However, When we compiled high-level language. RISC CPU need more instructions than CISC CPU.•CISC are complex but it doesn’t necessarily increase the cost. CISC processors are backward compactable.Why RISC is betterThe 80/20 rule: Analysis of the instruction mix generated by CISC compilers, shows that more than 80% of the instructions generated and executed used only 20% of an instruction set. It wasan obvious conclusion that if this 20% of instruction was speeded up, the performance benefits would be far greater. Further analysis shows that these instructions tend to perform the simpler operationsand use only the simpler addressing modes. For the CISC machine, all the effort invested in processor design to provide complex instructions and thereby reduce the compiler workload was being wasted. .•Less cost: Since only the simpler instructions are needed, the processor hardware required to implement them could be reduced in complexity. Therefor it should be possible to design a more performance processor with less cost. •Good performance: With a simpler instruction set, it should possible for a processor to execute its instruction in a single clock cycle. Higher performance can be achieved.Pipelining: A key RISC techniqueRISC designers are concerned primarily with creating the fastest chip possible, and so they use a number of techniques, including pipelining. Pipelining is a design technique where the computer's hardware processes more than one instruction at a time, and doesn't wait for one instruction to complete before starting the next.The advantages of RISCImplementing a processor with a simplified instruction set design provides several advantages over implementing a comparable CISC design: (1) Speed. Since a simplified instruction set allows for a pipelined, superscalar design RISC processors often achieve 2 to 4 times the performance of CISC processors using comparable semiconductor technology and the same clock rates. (2) Simpler hardware. Because the instruction set of a RISC processor is so
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