ASIC Back End Design Lecture given by Saadat Khan BAE Systems Slides prepared by Jamie Bernard BAE Systems Agenda Introduction Design Flow Overview Floorplan Timing Driven Placement Clock Tree Synthesis Routing Verification Design Example Introduction Introduction Technological Advances 19th Century Steel 20th Century Silicon Growth in Microelectronic Silicon Technology Moore s Law of transistors double 18 months One Transistor Small Scale Integration SSI Multiple Devices Transistor Resistor Diodes Possibility to create more than one logic gate Inverter etc Large Scale Integration LSI Systems with at least 1000 logic gates Several thousand transistors Very Large Scale Integration Millions to hundreds of millions of transistors Microprocessors Intel indicates that dual core processors will soon exist that contain 1 billion transistors Introduction Manual Human design can occur with small number of transistors As number of transistors increase through SSI and VLSI the amount of evaluation and decision making would become overwhelming Trade offs Maintaining performance requirements Power Speed Area Design and implementation times become impractical How does one create a complex electronic design consisting of millions of transistors Automate the Process using Computer Aided Design CAD Tools Introduction CAD tools provide several advantages Ability to evaluate complex conditions in which solving one problem creates other problems Use analytical methods to assess the cost of a decision Use synthesis methods to help provide a solution Allows the process of proposing and analyzing solutions to occur at the same time Electronic Design Automation Using CAD tools to create complex electronic designs ECAD Several companies who specialize in EDA Cadence Design Systems Magma Design Automation Inc Synopsys CAD Tools Allow Large Problems to be Solved Design Flow Design Flow Overview Generic VLSI Design Flow from System Specification to Fabrication and Testing Steps prior to Circuit Physical design are part of the FRONT END flow Physical Level Design is part of the BACKEND flow Physical Design is also known as Place and Route CAD tools are involved in all stages of VLSI design flow Different tools can be used at different stages due to EDA common data formats Synopsys CAD tool for Physical Design is called Astro What does Astro do Where does the Gate Level Netlist come from 1st Input to Astro Standard Cell Library 2nd Input to Astro Pre designed collection of logic functions OR AND XOR etc Contains both Layout and Abstract views Layout CEL contains drawn mask layers required for fabrication Abstract FRAM contains only minimal data needed for Astro Timing information Cell Delay Pin Capacitance Common height for placement purposes Basic Devices and Interconnect Integrated circuits are built out of active and passive components also called devices Active devices Transistors Diodes Passive devices Resistors Capacitors Devices are connected together with polysilicon or metal interconnect Interconnect can add unwanted or parasitic capacitance resistance and inductance effects Device types and sizes are process or technology specific The focus here is on CMOS technology 38 Transistor or Device Representation CMOS Inverter Example VDD PMOS IN OUT OUT IN NMOS GND Gate Schematic Transistor or Device View Gates Gatesare aremade madeup upof of active activedevices devicesor ortransistors transistors 37 What is Physical Layout CMOS Inverter Example VDD VDD PMOS PMOS OUT IN IN OUT NMOS NMOS GND GND Transistor or Device View Physical or Layout View Physical Layout Topography of devices and interconnects made up of polygons that represent different layers of material 39 Process of Device Fabrication Devices are fabricated vertically on a silicon substrate wafer by layering different materials in specific locations and shapes on top of each other Each of many process masks defines the shapes and locations of a specific layer of material diffusion polysilicon metal contact etc Mask shapes derived from the layout view are transformed to silicon via photolithographic and chemical processes Silicon Substrate Layout or Mask aerial view Wafer cross sectional view 40 Wafer Representation of Layout Polygons 0 25 um Input PMOS VDD Output GND NMOS Aerial or Layout View Wafer Cross sectional View Example of complimentary devices in 0 25 um CMOS technology or process 41 Contacts Connecting Metal 1 to Poly Diff n Diffusion Poly and Metal layers are separated by insulating oxide Connecting from Poly or Diffusion to Metal 1 requires a contact or cut Cut or Contact a hole in the oxide Metal 1 Oxide insulation Metal 1 Poly Diffusion Diffusion VDD IN GND 49 What is meant by 0 xx um Technology Gate or Channel Dimensions L and W L Length Length L W Widt h G A T E Narrow er Width Lower current throug h channe l G A T E Width W Wider Width Higher current throug h channe l In CMOS Technology the um or nm dimension refers to the channel length a minimum dimension which is fixed for most devices in the same library Current flow or drive strength of the device is proportional to W L Device size or area is proportional to W x L 42 L 0 5 um 2L Comparing Technologies L 0 25 um 2L W 3 um 2L 2L W 1 5 um A 0 5 um Technology B 0 25 um Technology Area Comparison The drive strength of both devices is the same W L 6 The diffusion area 5xLxW of A is 4x that of B 43 Relative Device Drive Strengths 0 25 um IN 0 25 um L 0 25 um IN 3 um W 1 5 um IN OUT OUT GND 1X NMOS W L 6 1 5 um GND 2X NMOS W L 12 OUT GND 2X NMOS W L 6 6 To double the drive strength of a device double the channel width W or connect two 1X devices in parallel The latter approach keeps the height at a fixed or standard height 44 Gate Drive Strength Example inv2 inv1 2x 1x PMOS transistor Input Output NMOS transistor Parallel PMOS transistors Input Output Parallel NMOS transistors Each gate in the library is represented by multiple cells with different drive strengths for effective speed vs area optimization 45 Drive Buffering Rules Max Transition Cap Maximum Transition Rule Violation After Optimization 1x Before Optimization Upsized Driver or Added Buffers 1x 2x 1x 1x Maximum Transition Rule Met 46 Timing Constraints 3rd Input to Astro Derived from system specifications and implementation of design Identical to timing constraints used during logic synthesis Common constraints in electronic designs Clock Speed Frequency Input Output Delays associated with I O signals Multicycle Paths
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