ECE 448 Lecture 13 Advanced Testbenches ECE 448 FPGA and ASIC Design with VHDL George Mason University Sources Sundar Rajan Essential VHDL RTL Synthesis Done Right Chapter 14 starting from Design Verification handout distributed in class ECE 448 FPGA and ASIC Design with VHDL 2 Simple Testbench Processes Generating Input Stimuli Design Under Test DUT Outputs Observed as Timing Waveforms ECE 448 FPGA and ASIC Design with VHDL 3 Advanced Testbench Processes Generating Input Stimuli Process Comparing Actual Outputs vs Expected Outputs Design Under Test DUT Yes No Design Correct Incorrect ECE 448 FPGA and ASIC Design with VHDL 4 Possible Sources of Expected Outputs VHDL Design Source Actual Outputs of Representative Inputs Manual Calculations Inputs or Expected Outputs Reference Software Implementation C Java Matlab ECE 448 FPGA and ASIC Design with VHDL 5 Test vectors Set of pairs Input i Expected Output i Input 1 Expected Output 1 Input 2 Expected Output 2 Input N Expected Output N Test vectors can be defined in the testbench source file stored in a data file ECE 448 FPGA and ASIC Design with VHDL 6 Asserts Reports ECE 448 FPGA and ASIC Design with VHDL 7 Assert Assert is a non synthesizable statement whose purpose is to write out messages on the screen when problems are found during simulation Depending on the severity of the problem The simulator is instructed to continue simulation or halt ECE 448 FPGA and ASIC Design with VHDL 8 Assert syntax ASSERT condition REPORT message SEVERITY severity level The message is written when the condition is FALSE Severity level can be Note Warning Error default or Failure ECE 448 FPGA and ASIC Design with VHDL 9 Assert Examples assert initial value max value report initial value too large severity error assert packet length 0 report empty network packet received severity warning assert false report Initialization complete severity note ECE 448 FPGA and ASIC Design with VHDL 10 Report syntax REPORT message SEVERITY severity level The message is always written Severity level can be Note default Warning Error or Failure ECE 448 FPGA and ASIC Design with VHDL 11 Report Examples report Initialization complete report Current time time image now report Incorrect branch severity error ECE 448 FPGA and ASIC Design with VHDL 12 Report Examples library IEEE use IEEE STD LOGIC 1164 all entity example 1 tb is end example 1 tb architecture behavioral of example 1 tb is signal clk std logic 0 begin clk not clk after 100 ns process begin wait for 1000 ns report Initialization complete report Current time time image now wait for 1000 ns report SIMULATION COMPLETED severity failure end process end behavioral ECE 448 FPGA and ASIC Design with VHDL 13 Records ECE 448 FPGA and ASIC Design with VHDL 14 Records type opcodes is add sub and or type reg number is range 0 to 8 type instruction is record opcode opcodes source reg1 reg number source reg2 reg number dest reg reg number end record instruction constant add instr 1 3 instruction opcode add source reg1 dest reg 1 source reg2 3 ECE 448 FPGA and ASIC Design with VHDL 15 Variables ECE 448 FPGA and ASIC Design with VHDL 16 Variable Example 1 LIBRARY ieee USE ieee std logic 1164 all ENTITY Numbits IS PORT X IN STD LOGIC VECTOR 15 DOWNTO 0 Count OUT INTEGER RANGE 0 TO 16 END Numbits ECE 448 FPGA and ASIC Design with VHDL 17 Variable Example 2 ARCHITECTURE Behavior OF Numbits IS BEGIN PROCESS X count the number of bits in X equal to 1 VARIABLE Tmp INTEGER BEGIN Tmp 0 FOR i IN 15 DOWNTO 0 LOOP IF X i 1 THEN Tmp Tmp 1 END IF END LOOP Count Tmp END PROCESS END Behavior ECE 448 FPGA and ASIC Design with VHDL 18 Variables features Can only be declared within processes and subprograms functions procedures Initial value can be explicitly specified in the declaration When assigned take an assigned value immediately Variable assignments represent the desired behavior not the structure of the circuit Should be avoided or at least used with caution in a synthesizable code ECE 448 FPGA and ASIC Design with VHDL 19 Using Arrays of Test Vectors In Testbenches ECE 448 FPGA and ASIC Design with VHDL 20 Testbench 1 LIBRARY ieee USE ieee std logic 1164 all ENTITY sevenSegmentTB is END sevenSegmentTB ARCHITECTURE testbench OF sevenSegmentTB IS COMPONENTsevenSegment PORT bcdInputs IN STD LOGIC VECTOR 3 DOWNTO 0 seven seg outputs OUT STD LOGIC VECTOR 6 DOWNTO 0 end COMPONENT CONSTANT PropDelay time 40 ns CONSTANT SimLoopDelay time 10 ns ECE 448 FPGA and ASIC Design with VHDL 21 Testbench 2 TYPE vector IS RECORD bcdStimulus STD LOGIC VECTOR 3 downto 0 sevSegOut STD LOGIC VECTOR 6 downto 0 END RECORD CONSTANT NumVectors INTEGER 10 TYPE vectorArray is ARRAY 0 TO NumVectors 1 OF vector CONSTANT vectorTable vectorArray bcdStimulus 0000 sevSegOut 0000001 bcdStimulus 0001 sevSegOut 1001111 bcdStimulus 0010 sevSegOut 0010010 bcdStimulus 0011 sevSegOut 0000110 bcdStimulus 0100 sevSegOut 1001100 bcdStimulus 0101 sevSegOut 0100100 bcdStimulus 0110 sevSegOut 0100000 bcdStimulus 0111 sevSegOut 0001111 bcdStimulus 1000 sevSegOut 0000000 bcdStimulus 1001 sevSegOut 0000100 ECE 448 FPGA and ASIC Design with VHDL 22 Testbench 3 SIGNAL StimInputs SIGNAL CaptureOutputs STD LOGIC VECTOR 3 downto 0 STD LOGIC VECTOR 6 downto 0 BEGIN u1 sevenSegment PORT MAP bcdInputs StimInputs seven seg outputs CaptureOutputs ECE 448 FPGA and ASIC Design with VHDL 23 Testbench 4 LoopStim PROCESS BEGIN FOR i in 0 TO NumVectors 1 LOOP StimInputs vectorTable i bcdStimulus WAIT FOR PropDelay ASSERT CaptureOutputs vectorTable i sevSegOut REPORT Incorrect Output SEVERITY error WAIT FOR SimLoopDelay END LOOP ECE 448 FPGA and ASIC Design with VHDL 24 Testbench 5 WAIT END PROCESS END testbench ECE 448 FPGA and ASIC Design with VHDL 25 File I O ECE 448 FPGA and ASIC Design with VHDL 26 Design Under Test 1 LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all ENTITY loadCnt IS PORT data IN STD LOGIC VECTOR 7 DOWNTO 0 load IN STD LOGIC clk IN STD LOGIC rst IN STD LOGIC q OUT STD LOGIC VECTOR 7 DOWNTO 0 END loadCnt ECE 448 FPGA and ASIC Design with VHDL 27 Design Under Test 2 ARCHITECTURE rtl OF loadCnt IS SIGNAL cnt STD LOGIC VECTOR 7 DOWNTO 0 BEGIN counter PROCESS clk rst BEGIN IF rst 1 THEN cnt OTHERS 0 ELSIF clk event AND clk 1 THEN IF load 1 THEN cnt data ELSE cnt cnt 1 END IF END IF END PROCESS q cnt END rtl ECE 448 FPGA and ASIC Design with VHDL 28 Test vector file 1 Format is Rst Load Data Q load the counter to all 1s 0 1 11111111 11111111 reset the counter 1
View Full Document
Unlocking...