Measuring the Gap Between FPGAs and ASICs Ian Kuon and Jonathan Rose The Edward S Rogers Sr Department of Electrical and Computer Engineering University of Toronto Toronto ON ikuon jayar eecg utoronto ca ABSTRACT 1 In the early stages of system design when system architects choose their implementation medium they often choose between FPGAs and ASICs Such decisions are based on the di erences in cost which is related to area performance and power consumption between these implementation media but to date there have been few attempts to quantify these di erences A system architect can use these measurements to assess whether implementation in an FPGA is feasible These measurements can also be useful for those building ASICs that contain programmable logic by quantifying the impact of leaving part of a design to be implemented in the programmable fabric This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density circuit speed and power consumption We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to FPGA makers on the de ciencies to attack and thereby improve FPGAs In the paper we describe the methodology by which the measurements were obtained and we show that for circuits containing only combinational logic and ip ops the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40 Modern FPGAs also contain hard blocks such as multiplier accumulators and block memories and we nd that these blocks reduce this average area gap signi cantly to as little as 21 The ratio of critical path delay from FPGA to ASIC is roughly 3 to 4 with less in uence from block memory and hard multipliers The dynamic power consumption ratio is approximately 12 times and with hard blocks this gap generally becomes smaller 2 FPGA makers seeking to improve FPGAs can gain insight by quantitative measurements of these metrics particularly when it comes to understanding the bene t of less programmable but more e cient hard heterogeneous blocks such as block memory 3 17 28 multipliers accumulators 3 17 28 and multiplexers 28 that modern FPGAs often employ In this paper we focus on a comparison between a 90 nm CMOS SRAM programmable FPGA and a 90 nm CMOS standard cell technology We chose an SRAM based FPGA because that approach by far dominates the market and it was necessary to limit the scope of comparison in order to make this work tractable Similarly standard cells 8 21 are currently the dominant choice in ASIC implementations versus pure gate arrays and the newer structured ASIC platforms 18 19 We present these measurements knowing that some of the methodology used will be controversial We will carefully describe the comparison process so that readers can form their own opinions of the validity of the result As always the set of benchmarks we use are highly in uential on the results and indeed any given FPGA vs ASIC comparison can vary signi cantly based on the application as our results show Since we perform measurements using a large set of designs it was not feasible to individually optimize each design and it is likely that manual optimizations or greater tuning of the tools could yield improved results for any individual design however this is true for both the ASIC and FPGA platforms We believe our results are more meaningful than past comparisons because we do consider a range of benchmarks instead of focusing on just a single design as has been done in most past analyses This paper is organized as follows Section 2 describes previous work on measuring the gap between FPGAs and ASICs Section 3 details the experimental methodology we Categories and Subject Descriptors B 7 Integrated Circuits Types and Design Styles General Terms Design Performance Measurement Keywords FPGA ASIC Area Comparison Delay Comparison Power Comparison 1 INTRODUCTION We were motivated to measure the area performance and power consumption gap between eld programmable gate arrays FPGAs and standard cell application speci c integrated circuits ASICs for the following reasons Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page To copy otherwise to republish to post on servers or to redistribute to lists requires prior specific permission and or a fee FPGA 06 February 22 24 2006 Monterey California USA Copyright 2006 ACM 1 59593 292 5 06 0002 5 00 21 use in this work The approach is a fundamentally empirical one in which the same circuits are implemented through two computer aided design CAD ows which are described in Sections 4 and 5 Section 6 gives a precise de nition of the comparison metrics Section 7 presents the comparison results and Section 8 concludes the paper paring more circuits and using an actual commercial FPGA for the comparison Compton and Hauck 11 have also measured the area differences between FPGA and standard cell designs They implemented multiple circuits from eight di erent application domains including areas such as radar and image processing on the Xilinx Virtex II FPGA in standard cells on a 0 18 m CMOS process from TSMC and on a custom con gurable platform Since the Xilinx Virtex II is designed in 0 15 m CMOS technology the area results are scaled up to allow direct comparison with 0 18 m CMOS Using this approach they found that the FPGA implementation is only 7 2 times larger on average than a standard cell implementation The authors believe that one of the key factors in narrowing this gap is the availability of heterogeneous blocks such as memory and multipliers in modern FPGAs and in our work we quantify these claims While the present work aims to measure the gap between FPGAs and ASICs it is noteworthy that the area speed and power penalty of FPGAs is even larger when compared to the best possible custom implementation using full custom design It has been observed that full custom designs tend to be 3 to 8 times faster than comparable standard cell ASIC designs 8 In terms of area a full custom design methodology has been found to achieve 14 5 times greater density than a standard cell ASIC methodology 12 Finally the power consumption of standard cell designs has been
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