ECE 448 Lecture 4 Structural Design Style Behavioral Design Style Registers and Counters ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 6 Combinational Circuit Building Blocks sections 6 6 5 6 6 7 optional Chapter 5 5 Design of Arithmetic Circuits Using CAD Tools Chapter 7 Flip Flops Registers Counters and a Simple Processor 7 14 optional ECE 448 FPGA and ASIC Design with VHDL 2 Optional Reading Sundar Rajan Essential VHDL RTL Synthesis Done Right Chapter 3 Gates Decoders and Encoders Chapter 4 Registers and Latches see errata at http www vahana com bugs htm ECE 448 FPGA and ASIC Design with VHDL 3 Register Transfer Level RTL Design Description Combinational Logic Combinational Logic Registers ECE 448 FPGA and ASIC Design with VHDL 4 Structural Design Style ECE 448 FPGA and ASIC Design with VHDL 5 VHDL Design Styles VHDL Design Styles dataflow Concurrent statements structural Components and interconnects ECE 448 FPGA and ASIC Design with VHDL behavioral Sequential statements Registers counters 6 Structural VHDL Major instructions component instantiation port map generate scheme for component instantiations for generate component instantiation with generic generic map port map ECE 448 FPGA and ASIC Design with VHDL 7 Structural VHDL Major instructions component instantiation port map generate scheme for component instantiations for generate component instantiation with generic generic map port map ECE 448 FPGA and ASIC Design with VHDL 8 Circuit built of medium scale components s 0 r 0 0 r 1 1 p 0 p 1 r 2 p 2 r 3 w0 w1 w2 w3 r 4 0 r 5 1 p 3 priority y0 q 0 q 1 y1 z ena w 0 w 1 En y 0 y 1 y 2 y 3 z 0 z 1 z 2 z 3 dec2to4 s 1 ECE 448 FPGA and ASIC Design with VHDL 9 2 to 1 Multiplexer s w 0 0 w 1 1 f a Graphical symbol ECE 448 FPGA and ASIC Design with VHDL s f 0 w 0 1 w 1 b Truth table 10 VHDL code for a 2 to 1 Multiplexer LIBRARY ieee USE ieee std logic 1164 all ENTITY mux2to1 IS PORT w0 w1 s f END mux2to1 IN OUT STD LOGIC STD LOGIC ARCHITECTURE dataflow OF mux2to1 IS BEGIN f w0 WHEN s 0 ELSE w1 END dataflow ECE 448 FPGA and ASIC Design with VHDL 11 Priority Encoder w0 y0 w1 y1 w2 z w3 w3 w2 w1 w0 0 0 0 0 1 0 0 0 1 x ECE 448 FPGA and ASIC Design with VHDL 0 0 1 x x 0 1 x x x y1 y0 z d 0 0 1 1 0 1 1 1 1 d 0 1 0 1 12 VHDL code for a Priority Encoder LIBRARY ieee USE ieee std logic 1164 all ENTITY priority IS PORT w IN y OUT z OUT END priority STD LOGIC VECTOR 3 DOWNTO 0 STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC ARCHITECTURE dataflow OF priority IS BEGIN y 11 WHEN w 3 1 ELSE 10 WHEN w 2 1 ELSE 01 WHEN w 1 1 ELSE 00 z 0 WHEN w 0000 ELSE 1 END dataflow ECE 448 FPGA and ASIC Design with VHDL 13 2 to 4 Decoder En w w 1 0 y y y y 0 1 2 3 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 x x 0 0 0 0 a Truth table ECE 448 FPGA and ASIC Design with VHDL w 0 w 1 En y 0 y 1 y 2 y 3 b Graphical symbol 14 VHDL code for a 2 to 4 Decoder LIBRARY ieee USE ieee std logic 1164 all ENTITY dec2to4 IS PORT w IN En IN y OUT END dec2to4 STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC STD LOGIC VECTOR 0 TO 3 ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw STD LOGIC VECTOR 2 DOWNTO 0 BEGIN Enw En w WITH Enw SELECT y 1000 WHEN 100 0100 WHEN 101 0010 WHEN 110 0001 WHEN 111 0000 WHEN OTHERS END dataflow ECE 448 FPGA and ASIC Design with VHDL 15 Circuit built of medium scale components s 0 r 0 0 r 1 1 p 0 p 1 r 2 p 2 r 3 w0 w1 w2 w3 r 4 0 r 5 1 p 3 priority y0 q 0 q 1 y1 z ena w 0 w 1 En y 0 y 1 y 2 y 3 z 0 z 1 z 2 z 3 dec2to4 s 1 ECE 448 FPGA and ASIC Design with VHDL 16 Structural description example 1 LIBRARY ieee USE ieee std logic 1164 all ENTITY priority resolver IS PORT r IN STD LOGIC VECTOR 5 DOWNTO 0 s IN STD LOGIC VECTOR 1 DOWNTO 0 z OUT STD LOGIC VECTOR 3 DOWNTO 0 END priority resolver ARCHITECTURE structural OF priority resolver IS SIGNAL p STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL q STD LOGIC VECTOR 1 DOWNTO 0 SIGNAL ena STD LOGIC ECE 448 FPGA and ASIC Design with VHDL 17 Structural description example 2 COMPONENT mux2to1 PORT w0 w1 s f END COMPONENT IN OUT COMPONENT priority PORT w IN y OUT z OUT END COMPONENT STD LOGIC VECTOR 3 DOWNTO 0 STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC COMPONENT dec2to4 PORT w IN En IN y OUT END COMPONENT STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC STD LOGIC VECTOR 0 TO 3 ECE 448 FPGA and ASIC Design with VHDL STD LOGIC STD LOGIC 18 Structural description example 3 BEGIN u1 mux2to1 PORT MAP w0 r 0 w1 r 1 s s 0 f p 0 p 1 r 2 p 1 r 3 u2 mux2to1 PORT MAP w0 r 4 w1 r 5 s s 1 f p 3 u3 priority PORT MAP w p y q z ena u4 dec2to4 PORT MAP w q En ena y z END structural ECE 448 FPGA and ASIC Design with VHDL 19 Named association connectivity recommended in majority of cases prevents ommisions and mistakes COMPONENT dec2to4 PORT w IN En IN y OUT END COMPONENT STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC STD LOGIC VECTOR 0 TO 3 u4 dec2to4 PORT MAP w q En ena y z ECE 448 FPGA and ASIC Design with VHDL 20 Positional association connectivity allowed especially for the cases of small number of ports multiple instantiations of the same component in regular structures COMPONENT dec2to4 PORT w IN En IN y OUT END COMPONENT STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC STD LOGIC VECTOR 0 TO 3 u4 dec2to4 PORT MAP w En y ECE 448 FPGA and ASIC Design with VHDL 21 Structural description with positional association connectivity BEGIN u1 mux2to1 PORT MAP r 0 r 1 s 0 p 0 p 1 r 2 p 1 r 3 u2 mux2to1 PORT MAP r 4 r 5 s 1 p 3 u3 priority PORT …
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