Lecture 8 RTL Design Methodology MIN MAX AVR Example Required reading P Chu FPGA Prototyping by VHDL Examples Chapter 6 FSMD S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 10 2 Design Examples ECE 448 FPGA and ASIC Design with VHDL 2 Structure of a Typical Digital System Data Inputs Datapath Execution Unit Control Inputs Control Signals Controller Control Unit Status Signals Data Outputs Control Outputs Hardware Design with RTL VHDL Interface Pseudocode Datapath Controller Block diagram VHDL code Block diagram VHDL code State diagram or ASM chart VHDL code Steps of the Design Process 1 2 3 4 5 Text description Interface Pseudocode Block diagram of the Datapath Interface with the division into the Datapath and the Controller 6 ASM chart of the Controller 7 RTL VHDL code 8 Testbench 9 Debugging 10 Synthesis and implementation 11 Experimental testing Steps of the Design Process 1 2 3 4 5 Text description Interface Pseudocode Block diagram of the Datapath Interface with the division into the Datapath and the Controller 6 ASM chart of the Controller 7 RTL VHDL code 8 Testbench 9 Debugging 10 Synthesis and implementation 11 Experimental testing MIN MAX AVR Example Circuit Interface clk DONE reset in data in addr write START n n 5 MIN MAX AVR 2 out data out addr Interface Table Port Width Meaning clk 1 System clock reset 1 System reset clears internal registers in data n Input data bus in addr 5 Address of the internal memory where input data is stored write 1 Synchronous write control signal START 1 Starts the computations DONE 1 Asserted when all results are ready out data n Output data bus used to read results out addr 2 01 reading minimum 10 reading maximum 11 reading average
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