Experiment 7 VHDL Modeling of Embedded Microprocessors and Microcontrollers ECE 448 FPGA and ASIC Design with VHDL George Mason University Simple Microprocessor ECE 448 FPGA and ASIC Design with VHDL George Mason University Basic Architecture Control unit and datapath Note similarity to single purpose processor Key differences Datapath is general Control unit doesn t store the algorithm the algorithm is programmed into the memory Processor Control unit Datapath ALU Controller Control Status Registers PC IR I O Memory Source Vahid and Givargis Embedded System Design A Unified Hardware Software Introduction ECE 448 FPGA and ASIC Design with VHDL 3 Instruction Cycles PC 100 Fetch Decode Fetch Exec Store ops results clk Processor Control unit Datapath ALU Controller Control Status Registers 10 PC 100 IR load R0 M 500 R0 I O 100 load R0 M 500 101 inc R1 R0 102 store M 501 R1 ECE 448 and FPGA and Embedded ASIC Design with VHDL Source Vahid Givargis System Design A Unified Hardware Software Introduction Memory 500 501 R1 10 4 Architectural Considerations Clock frequency Inverse of clock period Must be longer than longest register to register delay in entire processor Memory access is often the longest Processor Control unit Datapath ALU Controller Control Status Registers PC ECE 448 and FPGA and Embedded ASIC Design with VHDL Source Vahid Givargis System Design A Unified Hardware Software Introduction IR I O Memory 5 A Simple Trivial Instruction Set Assembly instruct First byte Second byte Operation MOV Rn direct 0000 Rn direct Rn M direct MOV direct Rn 0001 Rn direct M direct Rn MOV Rn Rm 0010 Rn MOV Rn immed 0011 Rn ADD Rn Rm 0100 Rn Rm Rn Rn Rm SUB Rn Rm 0101 Rn Rm Rn Rn Rm JZ Rn relative 0110 Rn opcode Rm immediate relative M Rn Rm Rn immediate PC PC relative only if Rn is 0 operands ECE 448 and FPGA and Embedded ASIC Design with VHDL Source Vahid Givargis System Design A Unified Hardware Software Introduction 6 Addressing Modes Addressing mode Operand field Immediate Data Register direct Register file contents Memory contents Register address Data Register indirect Register address Memory address Direct Memory address Data Indirect Memory address Memory address Data Data ECE 448 and FPGA and Embedded ASIC Design with VHDL Source Vahid Givargis System Design A Unified Hardware Software Introduction 7 Sample Program C program int total 0 for int i 10 i 0 i total i next instructions Equivalent assembly program 0 MOV R0 0 total 0 1 MOV R1 10 i 10 2 MOV R2 1 constant 1 3 MOV R3 0 constant 0 Loop JZ R1 Next Done if i 0 5 ADD R0 R1 total i 6 SUB R1 R2 i 7 JZ R3 Loop Jump always Next next instructions ECE 448 and FPGA and Embedded ASIC Design with VHDL Source Vahid Givargis System Design A Unified Hardware Software Introduction 8 Architecture of a Simple Microprocessor Storage devices for each declared variable register file holds each of the variables Functional units to carry out the FSMD operations One ALU carries out every required operation Connections added among the components ports corresponding to the operations required by the FSM Unique identifiers created for every control signal Control unit To all input control signals Controller Next state and control logic state register 16 PCld PCinc PC IR From all output control signals Irld RFs 1 0 2x1 mux RFwa RFw RFwe RF 16 RFr1a RFr1e RFr2a RFr2e RFr1 RFr2 ALUs PCclr 2 Ms Datapath 1 3x1 mux A ALUz 0 ALU Mre Mwe Memory D Source Vahid and Givargis Embedded System Design A Unified Hardware Software Introduction ECE 448 FPGA and ASIC Design with VHDL 9 A Simple Microprocessor Reset PC 0 PCclr 1 Fetch IR M PC PC PC 1 MS 10 Irld 1 Mre 1 PCinc 1 Decode from states below o p 0 0 0 0 Mov1 RF rn M dir to Fetch RFwa rn RFwe 1 RFs 01 Ms 01 Mre 1 M dir RF rn to Fetch RFr1a rn RFr1e 1 Ms 01 Mwe 1 Mov3 M rn RF rm to Fetch RFr1a rn RFr1e 1 Ms 00 Mwe 1 0 0 0 1 Mov2 0 0 1 0 Mov4 0 0 1 1 Add 0 1 0 0 RF rn RF rn RF rm to Fetch RFwa rn RFwe 1 RFs 00 RFr1a rn RFr1e 1 RFr2a rm RFr2e 1 ALUs 00 RFwa rn RFwe 1 RFs 00 RFr1a rn RFr1e 1 RFr2a rm RFr2e 1 ALUs 01 PCld ALUz RFrla rn RFrle 1 RF rn RF rn RF rm to Fetch Jz 0 1 1 0 RFwa rn RFwe 1 RFs 10 0 1 0 1 RF rn imm to Fetch Sub PC RF rn 0 rel PC to Fetch FSMD Control unit FSM operations that replace the FSMD operations after a datapath is created Controller Next state and control logic state register 16 PCld PCinc PC IR To all input contro l signals From all output control signals Irld RFs 1 0 2x1 mux RFwa RFwe RFr1a RFw RF 16 RFr1e RFr2a RFr2e RFr1 RFr2 ALUs PCclr 2 Ms Datapath 1 3x1 mux A ALUz 0 ALU Mre Mwe Memory D You just built a simple microprocessor ECE 448 and FPGA and Embedded ASIC Design with VHDL Source Vahid Givargis System Design A Unified Hardware Software Introduction 10 PIC Microcontroller ECE 448 FPGA and ASIC Design with VHDL George Mason University PIC Microcontroller implemented inside of an FPGA device FPGA CLK PIC Controller PORTC PORTB RESET STROBE PORTC 0 PORTA 7 Seg Decoder Display ECE 448 FPGA and ASIC Design with VHDL PORTA 12 PIC Microcontroller Core MCLR CLK PROGRAM PICROM 256 x 12 Addr 8 P C CONTROL UNIT Address Bus Data DATA 12 REGFILE Instruction Decoder 8 4 CONSTANTS W Fsel 8 FSR OPCODES Data Bus ALU EXTENDED COMPUTATIONS ALU 4 PORTA 4 ECE 448 FPGA and ASIC Design with VHDL R8 R31 Din Dout 8 8 PORTB 8 8 PORTC 8 13 Flowchart of our PIC program RESET Set Port Directions Sum 0 Counter 0 Wait for a rising edge at Port C 0 Wait for a rising edge at Port C 0 N Port B Port A Sum Sum Port A Counter Counter 1 Y Counter 8 ECE 448 FPGA and ASIC Design with VHDL Port B Sum 3 downto 0 Wait for a rising edge at Port C 0 Port B Sum 7 downto 4 14 Selected Registers of PIC ADDR W Working Register Accumulator PC Program Counter 05 06 07 PORTA PORTB PORTC 08 09 0A R8 R9 R10 1E R30 1F R31 TRISA TRISB TRISC ECE 448 FPGA and ASIC Design with VHDL Bidirectional Input Output Ports Register File General Purpose Registers Direction Registers for Ports A B C 15 Selected PIC Instructions 1 MOVF f d MOVF f 1 f f 8 31 MOVF f 0 k 0 255 W MOVWF f MOVLW k W MOVWF f k MOVLW k f ECE 448 FPGA and ASIC Design with VHDL W 16 Selected PIC Instructions 2 0 CLRF f CLRF f f f 8 31 0 CLRW CLRW W ECE 448 FPGA and ASIC …
View Full Document
Unlocking...