Final Exam Spring 2007 May 10 2007 25 points Part II open books open notes 1 hr 45 minutes 5 questions 2x5 3x2 5 pt 17 5 points Problem 1 5 points Draw a block diagram of the execution unit of a circuit capable of storing a set of 32 8 bit unsigned integers in an internal memory and then computing the largest and the second largest number in this set and their respective positions within the set The circuit should be able to execute the following pseudocode and should be optimized for minimum latency i e execute as many operations as possible in parallel while s 0 initialize internal memory MEM end while largest 0 second largest 0 largest pos 0 second largest pos 0 for i 0 to 31 do if MEM i largest then second largest largest second largest pos largest pos largest MEM i largest pos i end if if MEM i largest and MEM i second largest then second largest MEM i second largest pos i end if end for Assume the following interface to your circuit Port clk Resetn DataIn RAdd Width 1 1 8 5 WrInit s Rd 1 1 1 largest second largest largest pos second largest pos Done 8 8 5 5 1 Meaning System clock System reset clears internal registers Active low Input data bus Address of the internal memory MEM where input data is stored Synchronous write control signal Operating mode 0 initialization 1 computations Read enable 0 high impedance on all output buses 1 valid outputs Largest number in the input set Second largest number in the input set Position of the largest number in the input set Position of the second largest number in the input set Asserted when all results are ready zero otherwise Problem 2 5 points 1 Draw an interface to the execution unit and control unit from Problem 1 2 Draw an ASM chart corresponding to the pseudocode from Problem 1 3 Express all operations in your ASM chart in terms of active values of control signals generated as outputs of the control unit and used as inputs in the execution unit Problem 3 2 5 points For the given below circuit implementing sorting of four n bit numbers determine values of all control signals listed in the table during the execution of the instructions given in the first column of the table Values in the last four columns should correspond to the values of the corresponding signals before the instruction takes effect and may be marked as UN unknown Clearly distinguish between a don t care value and an inactive 0 value of the control signals Instruction R3 DataIn i 0 i i 1 A R0 B R1 R2 B R3 A j i j j 1 DataOut R2 WrInit Wr Rd Int Csel Ain Bin LI EI LJ EJ RAdd Imux Ci Cj DataIn ABmux n 0 1 n WrInit RData Rin0 E Rin1 E R0 E Rin2 Rin3 E R1 R2 0 1 2 3 R3 Imux ABData Ain Bin E Rd E n Clock DataOut 1 Bout 0 A B BltA 0 2 2 LI L EI E R LJ L R Counter Q EJ E Counter Q Ci Cj Clock 2 k 2 zi k 1 zj 2 Csel 0 1 Cmux RAdd 2 2 Int 0 1 Imux 2 y0 w0 w1 y 1 Rin 0 Rin 1 y2 Rin 2 y3 Rin 3 WrInit Wr En 2 to 4 decoder Assume that after the initialization the circuit performs the following pseudocode for i 0 to k 2 do A Ri for j i 1 to k 1 do B Rj if B A then Ri B Rj A A Ri end if end for end for Problem 4 2 5 points Translate the following block diagram to RTL VHDL assuming that a generic memory and a generic register have been already defined for you in separate files Describe the remaining components using dataflow design style Provide the complete entity and architecture including the component declarations Problem 5 2 5 points Modify the code of the File I O testbench provided in your answer sheet in such a way that it can verify the operation of a multiplier accumulator that computes a sum of 256 products Xi Yi Assume that each multiplication takes 16 clock cycles to execute and an addition takes two clock cycles to execute Port Xi Yi clk reset load S Width 16 16 1 1 1 40 Meaning Operand Xi Operand Yi Clock Reset Load operands Output S Assume the following format of an input file load reset X Y load reset X0 Y0 load reset X1 Y1 load reset X255 Y255 expected sum Assume that Xi Yi and expected sum S are provided in the hexadecimal notation and that the first line of the input file is used to reset the internal sum
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