ECE 448 Lecture 14 Multipliers ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 10 2 3 Shift and Add Multiplier Chapter 10 2 5 Arithmetic Mean Chapter 10 2 6 Sort Operation ECE 448 FPGA and ASIC Design with VHDL 2 Shift and Add Multiplier ECE 448 FPGA and ASIC Design with VHDL 3 An algorithm for multiplication Decimal 13 11 13 13 143 Binary 1 1 0 1 Multiplicand A 1 0 1 1 Multiplier B 1101 1101 0000 1101 1 0 001111 Product a Manual method ECE 448 FPGA and ASIC Design with VHDL P 0 for i 0 to n 1 do if bi 1 then P P A end if Left shift A end for b Pseudo code 4 Expected behavior of the multiplier ECE 448 FPGA and ASIC Design with VHDL 5 LA 0 DataA n EA LB DataB n n L Shift left E register EB A L Shift right E register B Clock n 2n Datapath for the multiplier z Sum 0 2n 1 Psel b0 2n 0 2n DataP EP E Register 2n ECE 448 FPGA and ASIC Design with VHDL 6 Reset S1 P 0 Load A Load B 0 0 ASM chart for the multiplier s s 1 1 S2 S3 Shift left A Shift rightB B 0 P P A Done 1 0 0 b0 1 ECE 448 FPGA and ASIC Design with VHDL 7 Reset S1 Psel 0 EP 0 s ASM chart for the multiplier control circuit 1 0 s S3 S2 Psel 1 EA EB Done 1 z EP 1 0 0 b0 1 ECE 448 FPGA and ASIC Design with VHDL 8 VHDL code of multiplier circuit 1 LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all USE work components all ENTITY multiply IS GENERIC N INTEGER 8 NN INTEGER 16 PORT Clock IN STD LOGIC Resetn IN STD LOGIC LA LB s IN STD LOGIC DataA IN STD LOGIC VECTOR N 1 DOWNTO 0 DataB IN STD LOGIC VECTOR N 1 DOWNTO 0 P BUFFER STD LOGIC VECTOR N 1 DOWNTO 0 Done OUT STD LOGIC END multiply ECE 448 FPGA and ASIC Design with VHDL 9 VHDL code of multiplier circuit 2 ARCHITECTURE Behavior OF multiply IS TYPE State type IS S1 S2 S3 SIGNAL y State type SIGNAL Psel z EA EB EP Zero STD LOGIC SIGNAL B N Zeros STD LOGIC VECTOR N 1 DOWNTO 0 SIGNAL A Ain DataP Sum STD LOGIC VECTOR NN 1 DOWNTO 0 BEGIN FSM transitions PROCESS Resetn Clock BEGIN IF Resetn 0 THEN y S1 ELSIF Clock EVENT AND Clock 1 THEN CASE y IS WHEN S1 IF s 0 THEN y S1 ELSE y S2 END IF WHEN S2 IF z 0 THEN y S2 ELSE y S3 END IF WHEN S3 IF s 1 THEN y S3 ELSE y S1 END IF END CASE END IF END PROCESS ECE 448 FPGA and ASIC Design with VHDL 10 VHDL code of multiplier circuit 3 FSM outputs PROCESS y s B 0 BEGIN EP 0 EA 0 EB 0 Done 0 Psel 0 CASE y IS WHEN S1 EP 1 WHEN S2 EA 1 EB 1 Psel 1 IF B 0 1 THEN EP 1 ELSE EP 0 END IF WHEN S3 Done 1 END CASE END PROCESS ECE 448 FPGA and ASIC Design with VHDL 11 LA 0 DataA n EA LB DataB n n L Shift left E register EB A L Shift right E register B Clock n 2n Datapath for the multiplier z Sum 0 2n 1 Psel b0 2n 0 2n DataP EP E Register 2n ECE 448 FPGA and ASIC Design with VHDL 12 VHDL code of multiplier circuit 4 Define the datapath circuit Zero 0 N Zeros OTHERS 0 Ain N Zeros DataA ShiftA shiftlne GENERIC MAP N NN PORT MAP Ain LA EA Zero Clock A ShiftB shiftrne GENERIC MAP N N PORT MAP DataB LB EB Zero Clock B z 1 WHEN B N Zeros ELSE 0 Sum A P Define the 2n 2 to 1 multiplexers for DataP GenMUX FOR i IN 0 TO NN 1 GENERATE Muxi mux2to1 PORT MAP Zero Sum i Psel DataP i END GENERATE RegP regne GENERIC MAP N NN PORT MAP DataP Resetn EP Clock P END Behavior ECE 448 FPGA and ASIC Design with VHDL 13 Array Multiplier ECE 448 FPGA and ASIC Design with VHDL 14 Notation a Multiplicand ak 1ak 2 a1 a0 x Multiplier xk 1xk 2 x1 x0 p Product a x ECE 448 FPGA and ASIC Design with VHDL p2k 1p2k 2 p2 p1 p0 15 Unsigned Multiplication x ax0 20 a4 a3 a2 a1 a0 x4 x3 x2 x1 x0 a4x0 a3x0 a2x0 a1x0 a0x0 ax1 21 a4x1 a3x1 a2x1 a1x1 a0x1 ax2 22 a4x2 a3x2 a2x2 a1x2 a0x2 ax3 23 a4x3 a3x3 a2x3 a1x3 a0x3 a4x4 a3x4 a2x4 a1x4 a0x4 ax4 24 p9 p8 p7 p6 ECE 448 FPGA and ASIC Design with VHDL p5 p4 p3 p2 p1 p0 16 5 x 5 Array Multiplier ECE 448 FPGA and ASIC Design with VHDL 17 Array Multiplier Basic Cell x y cin FA cout ECE 448 FPGA and ASIC Design with VHDL s 18 Array Multiplier Modified Basic Cell si 1 am ci xn FA ci 1 ECE 448 FPGA and ASIC Design with VHDL si 19 5 x 5 Array Multiplier with modified cells ECE 448 FPGA and ASIC Design with VHDL 20 Pipelined 5 x 5 Multiplier ECE 448 FPGA and ASIC Design with VHDL 21 Array Multiplier Modified Basic Cell si 1 am ci xn FA Flip flops ECE 448 FPGA and ASIC Design with VHDL ci 1 si 22 Timing parameters definition units time from point point ns clock period T rising edge rising edge of clock ns clock frequency 1 clock period MHz delay latency time from input output throughput output bits time unit ECE 448 FPGA and ASIC Design with VHDL ns Mbits s 23 Latency top level entity 8 bits 8 bits input D Q Combinational Combinational Logic Logic clk D Combinational Combinational Logic Logic Q D clk Q output clk 100 MHz clk input 0 input output 1 i e time it takes from first input to first output second input to second output etc Latency is usually constant for a system but not always Also called input to output latency Count the number of rising edges of the clock output 0 Latency is the time between input n and output n input 2 unknown output input 1 In this example 3 rising edges from input to output latency is 3 cycles Latency is measured in clock cycles then translated to seconds In this example say clock period is 10 ns then latency is 30 ns ECE 448 FPGA and ASIC Design with VHDL 24 Throughput input top level entity 8 bits 8 bits D Q Combinational Combinational Logic Logic clk D Q Combinational Combinational Logic Logic clk D Q output clk clk input output unknown input 2 output 0 …
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