Introduction to FPGA board FPGA Implementation Tools ECE 449 Computer Design Lab George Mason University FPGA Design Flow ECE 449 Computer Design Lab George Mason University Design flow 1 Design and implement a simple unit permitting to speed up encryption with RC5 similar cipher with fixed key set on 8031 microcontroller Unlike in the experiment 5 this time your unit has to be able to perform an encryption algorithm by itself executing 32 rounds Specification Lab Experiments VHDL description Your Source Files Library IEEE use ieee std logic 1164 all use ieee std logic unsigned all Functional simulation entity RC5 core is port clock reset encr decr in std logic data input in std logic vector 31 downto 0 data output out std logic vector 31 downto 0 out full in std logic key input in std logic vector 31 downto 0 key read out std logic end AES core Synthesis ECE 449 Computer Design Lab Post synthesis simulation 3 Design flow 2 Implementation Timing simulation Configuration On chip testing ECE 449 Computer Design Lab 4 Synthesis ECE 449 Computer Design Lab George Mason University Synthesis Tools Synplify Pro Xilinx XST and others ECE 449 Computer Design Lab 6 Logic Synthesis VHDL description Circuit netlist architecture MLU DATAFLOW of MLU is signal A1 STD LOGIC signal B1 STD LOGIC signal Y1 STD LOGIC signal MUX 0 MUX 1 MUX 2 MUX 3 STD LOGIC begin A1 A when NEG A 0 else not A B1 B when NEG B 0 else not B Y Y1 when NEG Y 0 else not Y1 MUX 0 A1 and B1 MUX 1 A1 or B1 MUX 2 A1 xor B1 MUX 3 A1 xnor B1 with L1 L0 select Y1 MUX 0 when 00 MUX 1 when 01 MUX 2 when 10 MUX 3 when others end MLU DATAFLOW ECE 449 Computer Design Lab 7 Implementation ECE 449 Computer Design Lab George Mason University Implementation After synthesis the entire implementation process is performed by FPGA vendor tools ECE 449 Computer Design Lab 9 Implementation cont ECE 449 Computer Design Lab 10 Translation Synthesis Circuit netlist Electronic Design Interchange Format EDIF Timing Constraints Constraint Editor Native Constraint File NCF UCF User Constraint File Translation NGD ECE 449 Computer Design Lab Native Generic Database file 11 Sample UCF File NET clock LOC P8 NET control 0 LOC K4 NET control 1 LOC K3 NET control 2 LOC K2 NET reset LOC E11 NET segments 0 LOC R10 NET segments 1 LOC P10 NET segments 2 LOC M11 NET segments 3 LOC M6 NET segments 4 LOC N6 NET segments 5 LOC T7 NET segments 6 LOC R7 ECE 449 Computer Design Lab 12 Pin Assignment FPGA E11 P8 P10 K2 N6 CLOCK CONTROL 0 CONTROL 1 CONTROL 2 RESET LAB2 SEGMENTS 0 SEGMENTS 1 SEGMENTS 2 SEGMENTS 3 SEGMENTS 4 SEGMENTS 5 SEGMENTS 6 R10 M11 M6 K3 R7 K4 T7 ECE 449 Computer Design Lab 13 Constraints Editor ECE 449 Computer Design Lab 14 Circuit netlist ECE 449 Computer Design Lab 15 Mapping LUT0 LUT4 LUT1 FF1 LUT5 LUT2 FF2 LUT3 ECE 449 Computer Design Lab 16 Placing FPGA CLB SLICES ECE 449 Computer Design Lab 17 Routing FPGA Programmable Connections ECE 449 Computer Design Lab 18 Configuration Once a design is implemented you must create a file that the FPGA can understand This file is called a bit stream a BIT file bit extension The BIT file can be downloaded directly to the FPGA or can be converted into a PROM file which stores the programming information ECE 449 Computer Design Lab 19 Static Timing Analysis ECE 449 Computer Design Lab 20 Static Timing Analyzer Performs static analysis of the circuit performance Reports critical paths with all sources of delays Determines maximum clock frequency ECE 449 Computer Design Lab 21 Static Timing Analysis Critical Path The Longest Path From Outputs of Registers to Inputs of Registers tP logic in D Q D Q out clk tCritical tP FF tP logic tS FF ECE 449 Computer Design Lab 22 Static Timing Analysis Min Clock Period Length of The Critical Path Max Clock Frequency 1 Min Clock Period ECE 449 Computer Design Lab 23 Timing Characteristics of Combinational Circuits Combinational Circuits Are Characterized by Propagation Delays through logic components gates LUTs through interconnects routing delays LUT tp LUT LUT LUT tp routing Total propagation delay through combinational logic ECE 449 Computer Design Lab 24 Timing Characteristics of Combinational Circuits 2 Total Propagation Delay of Logic Depends on the Number of Logic Levels and Delays of Logic Components Number of logic levels is the number of logic components gates LUTs the signal propagates through Routing Delays Depend on Length of interconnects Fanout ECE 449 Computer Design Lab 25 Timing Characteristics of Combinational Circuits 3 Fanout Number of Inputs Connected to One Output Each inputs has its capacitance Fast switching of outputs with high fanout requires higher currents and strong drivers LUT LUT LUT ECE 449 Computer Design Lab LUT 26 Timing Characteristics of Combinational Circuits 4 In Current FPGAs Routing Delays typically account for 45 to 65 of the total path delays ECE 449 Computer Design Lab 27 Timing simulation after implementation ECE 449 Computer Design Lab 28 Timing vs functional simulation Simulation before synthesis is used to verify circuit functionality and may differ from the one after synthesis and implementation Implementation tool generates SDF Standard Delay Format as a standard delay file and the netlist for synthesized VHDL code with delays Generated netlist contains many component instantiation statements with library references ECE 449 Computer Design Lab 29 SDF file A part of the SDF file is shown below It indicates XOR gate delays low to high high to low of minimum typical and worst case timing DELAYFILE CELL CELLTYPE XOR INSTANCE U34 Z VTX DELAY INCREMENT DEVICE 01 0 385090 0 385090 0 385090 0 235177 0 235177 0 235177 0 385090 0 385090 0 385090 ECE 449 Computer Design Lab 30 Netlist from the synthesis tool library IEEE U30 MUX21L port map Z n71 A n67 B library TC200G n68 S n69 use IEEE std logic 1164 all U31 EN port map Z n67 A D1 B D0 use TC200G components all U32 IV port map Z n68 A n67 entity CONSYN is U33 EOP port map Z n69 A D6 B D7 port RSTn CLK D0 D1 D2 D3 D4 D5 U34 EO3 port map Z n70 A D3 B D2 D6 D7 in std logic FF OUT C D4 COMB OUT FF COMB OUT out U35 EO port map Z n72 A D5 B n70 std logic U36 EOP port map Z XOR8 A n72 end CONSYN B n71 architecture structural of CONSYN is U37 FA1A port map S n73 CO n76 CI D3 signal XOR8 FF n70 n71 n72 n73 n74 n75 A D2 B FF n76 n67 n68 n69 std logic U38 EO3 port map Z n74 A n68 B n73 begin C D4 FF OUT FF U39 EOP port map Z FF COMB OUT A D5 COMB OUT XOR8 B n74 FF reg FD2 port map Q FF QN
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