ECE 448 Lecture 10 VHDL Coding for Synthesis ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading S Lee Advanced Digital Logic Design Chapter 4 4 Synthesis Heuristics handout S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 6 Combinational Circuit Building Blocks sections 6 6 5 6 6 8 Chapter 5 5 Design of Arithmetic Circuits Using CAD Tools ECE 448 FPGA and ASIC Design with VHDL 2 Optional Reading Sundar Rajan Essential VHDL RTL Synthesis Done Right Chapter 5 Counters and Simple Arithmetic Functions ECE 448 FPGA and ASIC Design with VHDL 3 Non synthesizable VHDL ECE 448 FPGA and ASIC Design with VHDL 4 Delays Delays are not synthesizable Statements such as wait for 5 ns a b after 10 ns will not produce the required delay and should not be used in the code intended for synthesis ECE 448 FPGA and ASIC Design with VHDL 5 Initializations Declarations of signals and variables with initialized values such as SIGNAL a STD LOGIC 0 cannot be synthesized and thus should be avoided If present they will be ignored by the synthesis tools Use set and reset signals instead ECE 448 FPGA and ASIC Design with VHDL 6 Reports and asserts Reports and asserts such as report Initialization complete assert initial value max value report initial value too large severity error cannot be synthesized but they can be freely used in the code intended for synthesis They will be used during simulation and ignored during synthesis ECE 448 FPGA and ASIC Design with VHDL 7 Floating point operations Operations on signals and variables of the type real are not synthesizable by the current generation of synthesis tools ECE 448 FPGA and ASIC Design with VHDL 8 Synthesizable VHDL ECE 448 FPGA and ASIC Design with VHDL 9 Register Transfer Level RTL Design Description Combinational Logic Combinational Logic Registers ECE 448 FPGA and ASIC Design with VHDL 10 VHDL Design Styles VHDL Design Styles dataflow Concurrent statements structural behavioral Components and Sequential statements interconnects Registers synthesizable Shift registers Counters State machines and more if you are careful ECE 448 FPGA and ASIC Design with VHDL 11 Combinational Logic Synthesis for Beginners ECE 448 FPGA and ASIC Design with VHDL 12 Simple rules for beginners For combinational logic use only concurrent statements concurrent signal assignment conditional concurrent signal assignment when else selected concurrent signal assignment with select when generate scheme for equations for generate ECE 448 FPGA and ASIC Design with VHDL 13 Simple rules for beginners For circuits composed of simple logic operations logic gates simple arithmetic operations addition subtraction multiplication shifts rotations by a constant use concurrent signal assignment ECE 448 FPGA and ASIC Design with VHDL 14 Simple rules for beginners For circuits composed of multiplexers decoders encoders tri state buffers use conditional concurrent signal assignment when else selected concurrent signal assignment with select when ECE 448 FPGA and ASIC Design with VHDL 15 Left vs right side of the assignment Left side Right side when else with select Internal signals defined in a given architecture Ports of the mode out inout buffer ECE 448 FPGA and ASIC Design with VHDL Expressions including Internal signals defined in a given architecture Ports of the mode in inout buffer 16 Arithmetic operations Synthesizable arithmetic operations Addition Subtraction Comparisons Multiplication Division by a power of 2 2 6 equivalent to right shift Shifts by a constant SHL SHR ECE 448 FPGA and ASIC Design with VHDL 17 Arithmetic operations The result of synthesis of an arithmetic operation is a combinational circuit without pipelining The exact internal architecture used and thus delay and area of the circuit may depend on the timing constraints specified during synthesis e g the requested maximum clock frequency ECE 448 FPGA and ASIC Design with VHDL 18 Operations on Unsigned Numbers For operations on unsigned numbers USE ieee std logic unsigned all and signals inputs outputs of the type STD LOGIC VECTOR OR USE ieee std logic arith all and signals inputs outputs of the type UNSIGNED ECE 448 FPGA and ASIC Design with VHDL 19 Operations on Signed Numbers For operations on signed numbers USE ieee std logic signed all and signals inputs outputs of the type STD LOGIC VECTOR OR USE ieee std logic arith all and signals inputs outputs of the type SIGNED ECE 448 FPGA and ASIC Design with VHDL 20 Signed and Unsigned Types Behave exactly like STD LOGIC VECTOR plus they determine whether a given vector should be treated as a signed or unsigned number Require USE ieee std logic arith all ECE 448 FPGA and ASIC Design with VHDL 21 Integer Types Operations on signals variables of the integer types INTEGER NATURAL and their sybtypes such as TYPE day of month IS RANGE 0 TO 31 are synthesizable in the range 231 1 231 1 for INTEGERs and their subtypes 0 231 1 for NATURALs and their subtypes ECE 448 FPGA and ASIC Design with VHDL 22 Integer Types Operations on signals variables of the integer types INTEGER NATURAL are less flexible and more difficult to control than operations on signals variables of the type STD LOGIC VECTOR UNSIGNED SIGNED and thus are recommened to be avoided by beginners ECE 448 FPGA and ASIC Design with VHDL 23 Addition of Signed Numbers 1 LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic signed all ENTITY adder16 IS PORT Cin X Y S Cout Overflow END adder16 IN IN OUT OUT STD LOGIC STD LOGIC VECTOR 15 DOWNTO 0 STD LOGIC VECTOR 15 DOWNTO 0 STD LOGIC ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum STD LOGIC VECTOR 16 DOWNTO 0 BEGIN Sum 0 X Y Cin S Sum 15 DOWNTO 0 Cout Sum 16 Overflow Sum 16 XOR X 15 XOR Y 15 XOR Sum 15 END Behavior ECE 448 FPGA and ASIC Design with VHDL 24 Addition of Signed Numbers 2 LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic arith all ENTITY adder16 IS PORT Cin X Y S Cout Overflow END adder16 IN IN OUT OUT STD LOGIC SIGNED 15 DOWNTO 0 SIGNED 15 DOWNTO 0 STD LOGIC ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum SIGNED 16 DOWNTO 0 BEGIN Sum 0 X Y Cin S Sum 15 DOWNTO 0 Cout Sum 16 Overflow Sum 16 XOR X 15 XOR Y 15 XOR Sum 15 END Behavior ECE 448 FPGA and ASIC Design with VHDL 25 Addition of Signed Numbers 3 ENTITY adder16 IS PORT X Y S END adder16 IN OUT INTEGER RANGE 32768 TO 32767 INTEGER RANGE 32768 TO 32767 ARCHITECTURE Behavior OF adder16 IS BEGIN S X Y END Behavior ECE 448 FPGA and ASIC Design
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