Lab7demo Introduction to Celoxica DK Design Suite New Project Name new Project RC10 Select network location Select Xilinx Spartan 3 3L chip OK Build Configuration Go to Build Configurations Select Add button Name new configuration Lab7demo copy from EDIF Click OK Remove all other configurations except Lab7demo Close Change Project Setting Go to Project Settings Select General tab Rename Intermediate files and Output files to Lab7demo Change Project Setting cont Select Preprocessor tab Add USE RC10 to definitions Add Additional include directories C Program Files Celoxica PDK Hardware include Change Project Setting cont Select Chip tab Select Device xc3s1500l Package fg320 Speed Grade 4 Change Project Setting cont Select Linker tab Add Object Library modules stdlib hcl rc10 hcl pal rc10 hcl and other libraries as needed Add Additional Library path C Program Files Celoxica PDK Hardware lib Change Project Setting cont Select Build commands tab Under View Outputs Add following command Lab7demo Note Bit file is generated under Lab7demo folder Click on OK to save setting Change Project Setting cont Select Build commands tab Under View Commands Add following command in order cd Lab7demo Note this is to change to intermediate working folder Edifmake RC10 RC10 Note this command to build RC10 project beep Note this command beeps at the end of building Add Files to Project Add a new file with Project Add to Project New Handle C Note for this demo right click on RC10 chip and Add file to folder Choose Display7segment hcc download from the web Compile and Build Select configuration Lab7demo Click on Compile icon to compile the project Click on Build icon to build the project Verify Bitstream generation successfully Locate RC10 bit file under project folder RC10 Lab7demo Run bit file
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