ECE 448 Lecture 6 Mixing Design Styles Synthesis Modeling of circuits with regular structure ECE 448 FPGA and ASIC Design with VHDL George Mason University Mixing Design Styles Inside of an Architecture ECE 448 FPGA and ASIC Design with VHDL 2 VHDL Design Styles VHDL Design Styles dataflow Concurrent statements structural behavioral Components and Sequential statements interconnects Registers synthesizable ECE 448 FPGA and ASIC Design with VHDL Shift registers Counters State machines 3 Mixed Style Modeling architecture ARCHITECTURE NAME of ENTITY NAME is Here you can declare signals constants functions procedures Component declarations No variable declarations begin Concurrent statements Concurrent simple signal assignment Conditional signal assignment Selected signal assignment Generate statement Concurrent Statements Component instantiation statement Process statement inside process you can use only sequential statements end ARCHITECTURE NAME ECE 448 FPGA and ASIC Design with VHDL 4 PRNG Example 1 library IEEE use IEEE STD LOGIC 1164 all use work prng pkg all ENTITY PRNG IS PORT Coeff in std logic vector 4 downto 0 Load Coeff in std logic Seed in std logic vector 4 downto 0 Init Run in std logic Clk in std logic Current State out std logic vector 4 downto 0 END PRNG ARCHITECTURE mixed OF PRNG is signal Ands std logic vector 4 downto 0 signal Sin std logic signal Coeff Q std logic vector 4 downto 0 signal Shift5 Q std logic vector 4 downto 0 ECE 448 FPGA and ASIC Design with VHDL 5 PRNG Example 2 Data Flow G FOR I IN 0 TO 4 GENERATE Ands I Coeff Q I AND Shift5 Q I END GENERATE Sin Ands 0 XOR Ands 1 XOR Ands 2 XOR Ands 3 XOR Ands 4 Current State Shift5 Q Behavioral Coeff Reg PROCESS Clk BEGIN IF Clk EVENT and Clk 1 THEN IF Load Coeff 1 THEN Coeff Q Coeff END IF END IF END PROCESS Structural Shift5 Reg Shift5 PORT MAP D Seed Load Init Run Sin Sin Clock Clk Q Shift5 Q END mixed ECE 448 FPGA and ASIC Design with VHDL 6 Synthesis ECE 448 FPGA and ASIC Design with VHDL George Mason University Resources Required Reading Movie Demos Integrated Interfaces Active HDL with Synplify Integrated Synthesis and Implementation Active HDL Help ECE 448 FPGA and ASIC Design with VHDL 8 Design flow 1 Design and implement a simple unit permitting to speed up encryption with RC5 similar cipher with fixed key set on 8031 microcontroller Unlike in the experiment 5 this time your unit has to be able to perform an encryption algorithm by itself executing 32 rounds Specification Lab Experiments VHDL description Your Source Files Library IEEE use ieee std logic 1164 all use ieee std logic unsigned all Functional simulation entity RC5 core is port clock reset encr decr in std logic data input in std logic vector 31 downto 0 data output out std logic vector 31 downto 0 out full in std logic key input in std logic vector 31 downto 0 key read out std logic end AES core Synthesis ECE 448 FPGA and ASIC Design with VHDL Post synthesis simulation 9 Synthesis Tools Synplify Pro Xilinx XST and others ECE 448 FPGA and ASIC Design with VHDL 10 Logic Synthesis VHDL description Circuit netlist architecture MLU DATAFLOW of MLU is signal A1 STD LOGIC signal B1 STD LOGIC signal Y1 STD LOGIC signal MUX 0 MUX 1 MUX 2 MUX 3 STD LOGIC begin A1 A when NEG A 0 else not A B1 B when NEG B 0 else not B Y Y1 when NEG Y 0 else not Y1 MUX 0 A1 and B1 MUX 1 A1 or B1 MUX 2 A1 xor B1 MUX 3 A1 xnor B1 with L1 L0 select Y1 MUX 0 when 00 MUX 1 when 01 MUX 2 when 10 MUX 3 when others end MLU DATAFLOW ECE 448 FPGA and ASIC Design with VHDL 11 Features of synthesis tools Interpret RTL code Produce synthesized circuit netlist in a standard EDIF format Give preliminary performance estimates Display circuit schematic corresponding to EDIF netlist ECE 448 FPGA and ASIC Design with VHDL 12 Timing report after synthesis Performance Summary Worst slack in design 0 924 Requested Estimated Requested Estimated Starting Clock Frequency Frequency Period Period Slack System 85 0 MHz 86 4 MHz 11 765 11 572 0 193 Slack Estimated Clock Period Requested Clock Period Negative Slack means timing violations Positive Slack means positive margin before timing violation ECE 448 FPGA and ASIC Design with VHDL 13 Generate scheme for components ECE 448 FPGA and ASIC Design with VHDL 14 Structural VHDL Major instructions component instantiation port map component instantiation with generic generic map port map generate scheme for component instantiations for generate ECE 448 FPGA and ASIC Design with VHDL 15 Example 1 ECE 448 FPGA and ASIC Design with VHDL 16 Example 1 s0 s1 w0 w3 w4 s2 s3 w7 f w8 w11 w12 w15 ECE 448 FPGA and ASIC Design with VHDL 17 A 4 to 1 Multiplexer LIBRARY ieee USE ieee std logic 1164 all ENTITY mux4to1 IS PORT w0 w1 w2 w3 s IN f OUT END mux4to1 IN STD LOGIC STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC ARCHITECTURE Dataflow OF mux4to1 IS BEGIN WITH s SELECT f w0 WHEN 00 w1 WHEN 01 w2 WHEN 10 w3 WHEN OTHERS END Dataflow ECE 448 FPGA and ASIC Design with VHDL 18 Straightforward code for Example 1 LIBRARY ieee USE ieee std logic 1164 all ENTITY Example1 IS PORT w IN s IN f OUT END Example1 STD LOGIC VECTOR 0 TO 15 STD LOGIC VECTOR 3 DOWNTO 0 STD LOGIC ECE 448 FPGA and ASIC Design with VHDL 19 Straightforward code for Example 1 ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT w0 w1 w2 w3 IN STD LOGIC s IN STD LOGIC VECTOR 1 DOWNTO 0 f OUT STD LOGIC END COMPONENT SIGNAL m STD LOGIC VECTOR 0 TO 3 BEGIN Mux1 mux4to1 PORT MAP w 0 Mux2 mux4to1 PORT MAP w 4 Mux3 mux4to1 PORT MAP w 8 Mux4 mux4to1 PORT MAP w 12 Mux5 mux4to1 PORT MAP m 0 END Structure w 1 w 5 w 9 w 13 m 1 ECE 448 FPGA and ASIC Design with VHDL w 2 w 6 w 10 w 14 m 2 w 3 w 7 w 11 w 15 m 3 s 1 DOWNTO 0 m 0 s 1 DOWNTO 0 m 1 s 1 DOWNTO 0 m 2 s 1 DOWNTO 0 m 3 s 3 DOWNTO 2 f 20 Modified code for Example 1 ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT w0 w1 w2 w3 s f END COMPONENT IN IN OUT STD LOGIC STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC SIGNAL m STD LOGIC VECTOR 0 TO 3 BEGIN G1 FOR i IN 0 TO 3 GENERATE Muxes mux4to1 PORT MAP w 4 i w 4 i 1 w 4 i 2 w 4 i 3 s 1 DOWNTO 0 m i END GENERATE Mux5 mux4to1 PORT MAP m 0 m 1 m 2 m 3 s 3 DOWNTO 2 f END Structure ECE 448 FPGA and ASIC Design with VHDL 21 …
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