Lab 1 Introduction to Aldec Active HDL Implementing Combinational Logic in VHDL ECE 448 FPGA and ASIC Design with VHDL George Mason University Part 1 Introduction to Aldec Active HDL Example MLU MLU Block Diagram MUX 0 A1 A NEG A IN0 MUX 1 IN1 MUX 2 Y1 IN2 IN3 Y OUTPUT SEL1 SEL0 B B1 MUX 4 1 MUX 3 NEG B L1 L0 NEG Y Experiment 1 Problem 1 ALU of Motorola 68HC11 Register structure of MC6811 7 A 0 7 B 0 Accumulators A and B or Double Accumulator D 15 D 0 15 IX 0 X index register 15 IY 0 Y index register 15 SP 0 Stack Pointer 15 PC 0 Program Counter 0 Condition Code Register 7 CCR SXHINZVC Condition Code Register 7 CCR 0 SXHINZVC carry borrow overflow zero negative I interrupt mask half carry from bit 3 X interrupt mask stop disable Definition of the Condition Code Register flags 1 Zero flag Z Z 1 0 zero result if result 0 otherwise Negative flag N negative result N sign bit of the result R7 for an 8 bit result Definition of the Condition Code Register flags 2 Carry flag C C 1 0 out of range for unsigned numbers if result MAX UNSIGNED or result 0 otherwise where MAX UNSIGNED 28 1 for 8 bit results Overflow flag V V 1 0 out of range for signed numbers if result MAX SIGNED or result MIN SIGNED otherwise where MAX SIGNED 27 1 and MIN SIGNED 27 for 8 bit results Overflow for signed numbers 1 Indication of overflow Positive Positive Negative Negative Negative Positive Addressing modes of the ADDA instruction Immediate mode ADDA 5C Direct mode ADDA 1B A 5C A A 001B A Extended mode ADDA 6D00 A 6D00 A M Indexed mode ADDA 56 X ADDA 56 Y A IX 56 A A IY 56 A Assembly language vs machine code Assembly language mnemonic operands Machine code NEGB ADDA ADDA 4A 5B78 opcode operands 50 8B 4A BB 5B 78 Logic instructions NZVC 1 AND Acc M Acc AND A B 2 OR IMM DIR EXT IND 0 IMM DIR EXT IND 0 IMM DIR EXT IND 0 INH EXT IND 01 Acc M Acc ORA A B 3 XOR Acc M Acc EOR A B 4 complement COM A B COM X X Arithmetic instructions 1 1 addition Acc M Acc Acc M C Acc ADD A B ADC A B 2 subtraction Acc M Acc Acc M C Acc SUB A B SBC A B NZVC IMM DIR EXT IND IMM DIR EXT IND 3 negation X NEG A B NEG INH EXT IND Arithmetic instructions 2 NZVC 4 unsigned multiplication Ax B D MUL INH Alter data instructions NZVC 1 0 register CLR A B INH 01 00 EXT IND 01 00 2 0 memory CLR 3 increment X INC A B INC 4 decrement X DEC A B DEC INH EXT IND INH EXT IND Edit instructions Shifts 1 logical shift right 0 0 7 LSR A B LSR INH EXT IND 2 arithmetic shift right ASR A B ASR C NZVC 0 7 0 C INH EXT IND 3 arithmetic logical shift left C ASL A B LSL A B ASL LSL INH EXT IND 7 0 0 Edit instructions Rotations 1 rotation right ROR A B ROR 0 7 C INH EXT IND 2 rotation left C ROL A B ROL NZVC INH EXT IND 7 0 0 Part 2 Mini ALU Mnemonic Operation Opcode ADDAB R A B 0000 ADDAM R A M 0001 SUBAB R A B 0010 SUBAM R A M 0011 NOTA R NOT A 0100 NOTB R NOT B 0101 NOTM R NOT M 0110 ANDAB R A AND B 0111 ANDAM R A AND M 1000 ORAB R A OR B 1001 ORAM R A OR M 1010 XORAB R A XOR B 1011 XORAM R A XOR M 1100 opcode 4 4 A 4 B 4 M Mini ALU 4 R Block diagram Arithmetic Functions in VHDL 1 To use arithmetic operations involving std logic vectors you need to include the following library packages library ieee use ieee std logic 1164 all use ieee STD LOGIC UNSIGNED ALL Arithmetic Functions in VHDL 2 You can use standard operators to perform addition and subtraction signal A signal B signal C C A B STD LOGIC VECTOR 3 downto 0 STD LOGIC VECTOR 3 downto 0 STD LOGIC VECTOR 3 downto 0
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