Lecture 13 RTL Design Methodology Sorting Structure of a Typical Digital System Data Inputs Datapath Execution Unit Control Inputs Control Signals Controller Control Unit Status Signals Data Outputs Control Outputs Hardware Design with RTL VHDL Interface Pseudocode Datapath Controller Block diagram VHDL code Block diagram VHDL code State diagram or ASM chart VHDL code Steps of the Design Process 1 2 3 4 5 Text description Interface Pseudocode Block diagram of the Datapath Interface with the division into the Datapath and the Controller 6 ASM chart of the Controller 7 RTL VHDL code 8 Testbench 9 Debugging 10 Synthesis and implementation 11 Experimental testing Steps of the Design Process Practiced in Class Text description Interface Pseudocode Block diagram of the Datapath Interface with the division into the Datapath and the Controller 6 ASM chart of the Controller 7 RTL VHDL code 8 Testbench 9 Debugging 10 Synthesis and implementation 11 Experimental testing 1 2 3 4 5 Sorting Example Sorting Required Interface Clock Resetn DataIn RAdd N DataOut L WrInit S 0 initialization 1 computations Rd N Sort Done Simulation results for the sort operation 1 Loading the registers and starting sorting Simulation results for the sort operation 2 Completing sorting and reading out registers Sorting Example Before sorting address 0 1 2 3 Legend 3 2 4 1 During Sorting i 0 j 1 i 0 j 2 i 0 j 3 i 1 j 2 i 1 j 3 i 2 j 3 3 2 4 1 2 3 4 1 2 3 4 1 1 3 4 2 1 3 4 2 1 2 4 3 position of memory indexed by i i position of memory indexed by j After sorting 1 2 3 4 j Pseudocode wait for s 1 for i 0 to k 2 do A M i for j i 1 to k 1 do B M j if A B then M i B M j A A M i end if end for end for Done wait for s 0 go to the beginning DataIn ABMux RAdd N 0 1 Wr ADDR 1 RST Resetn Bin EN CLK Bout RST N N 0 LJ EJ Clock LD EN CLK RST L j 1 ABData Clock Clock L L i 0 CLK N EN CLK Resetn 1 0 Addr DOUT Ain RST Csel WE Clock Clock Int DIN We LD EN CLK LI EI WrInit Din WrInit L L N 1 0 Resetn Rd k 2 k 1 zi zj N B A A B AgtB DataOut Block diagram of the Datapath Resetn
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