Lecture 2 VHDL Refresher ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading P Chu FPGA Prototyping by VHDL Examples Chapter 1 Gate level combinational circuit S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 2 10 Introduction to VHDL ECE 448 FPGA and ASIC Design with VHDL 2 Recommended reading Wikipedia The Free On line Encyclopedia VHDL http en wikipedia org wiki VHDL Verilog http en wikipedia org wiki Verilog ECE 448 FPGA and ASIC Design with VHDL 3 Recommended reading Required for Lab 1 Opportunity for bonus points during the next two lectures P Chu FPGA Prototyping by VHDL Examples Chapter 3 RT level combinational circuit S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 6 Combinational circuit building blocks ECE 448 FPGA and ASIC Design with VHDL 4 Brief History of VHDL ECE 448 FPGA and ASIC Design with VHDL 5 VHDL VHDL is a language for describing digital hardware used by industry worldwide VHDL is an acronym for VHSIC Very High Speed Integrated Circuit Hardware Description Language ECE 448 FPGA and ASIC Design with VHDL 6 Genesis of VHDL State of art circa 1980 Multiple design entry methods and hardware description languages in use No or limited portability of designs between CAD tools from different vendors Objective shortening the time from a design concept to implementation from 18 months to 6 months ECE 448 FPGA and ASIC Design with VHDL 7 A Brief History of VHDL June 1981 Woods Hole Workshop July 1983 contract awarded to develop VHDL Intermetrics IBM Texas Instruments August 1985 VHDL Version 7 2 released December 1987 VHDL became IEEE Standard 1076 1987 and in 1988 an ANSI standard ECE 448 FPGA and ASIC Design with VHDL 8 Four versions of VHDL Four versions of VHDL IEEE 1076 1987 IEEE 1076 1993 most commonly supported by CAD tools IEEE 1076 2000 minor changes IEEE 1076 2002 minor changes ECE 448 FPGA and ASIC Design with VHDL 9 Verilog ECE 448 FPGA and ASIC Design with VHDL 10 Verilog Essentially identical in function to VHDL No generate statement Simpler and syntactically different C like Gateway Design Automation Co 1985 Gateway acquired by Cadence in 1990 IEEE Standard 1364 1995 Early de facto standard for ASIC programming Programming language interface to allow connection to non Verilog code ECE 448 FPGA and ASIC Design with VHDL 11 VHDL vs Verilog Government Developed Commercially Developed Ada based C based Strongly Type Cast Mildly Type Cast Case insensitive Case sensitive Difficult to learn Easier to Learn More Powerful Less Powerful ECE 448 FPGA and ASIC Design with VHDL 12 How to learn Verilog by yourself ECE 448 FPGA and ASIC Design with VHDL 13 Features of VHDL and Verilog Technology vendor independent Portable Reusable ECE 448 FPGA and ASIC Design with VHDL 14 VHDL Fundamentals ECE 448 FPGA and ASIC Design with VHDL 15 Naming and Labeling 1 VHDL is case insensitive Example Names or labels databus Databus DataBus DATABUS are all equivalent ECE 448 FPGA and ASIC Design with VHDL 16 Naming and Labeling 2 General rules of thumb according to VHDL 87 1 2 3 4 5 All names should start with an alphabet character a z or A Z Use only alphabet characters a z or A Z digits 0 9 and underscore Do not use any punctuation or reserved characters within a name etc Do not use two or more consecutive underscore characters within a name e g Sel A is invalid All names and labels in a given entity and architecture must be unique ECE 448 FPGA and ASIC Design with VHDL 17 Valid or invalid 7segment display A87372477424 Adder Subtractor reset And or gate AND OR NOT Kogge Stone Adder Ripple Carry Adder My adder ECE 448 FPGA and ASIC Design with VHDL 18 Free Format VHDL is a free format language No formatting conventions such as spacing or indentation imposed by VHDL compilers Space and carriage return treated the same way Example if a b then or if a b then or if a b then are all equivalent ECE 448 FPGA and ASIC Design with VHDL 19 Readability standards coding style Adopt readability standards based on one of the the two main textbooks Chu or Brown Vranesic Use coding style recommended in OpenCores Coding Guidelines linked from the course web page Strictly enforced by the lab instructors and myself Penalty points may be enforced for not following these recommendations ECE 448 FPGA and ASIC Design with VHDL 20 Comments Comments in VHDL are indicated with a double dash i e Comment indicator can be placed anywhere in the line Any text that follows in the same line is treated as a comment Carriage return terminates a comment No method for commenting a block extending over a couple of lines Examples main subcircuit Data in Data bus reading data from the input FIFO ECE 448 FPGA and ASIC Design with VHDL 21 Comments Explain Function of Module to Other Designers Explanatory Not Just Restatement of Code Locate Close to Code Described Put near executable code not just in a header ECE 448 FPGA and ASIC Design with VHDL 22 Design Entity ECE 448 FPGA and ASIC Design with VHDL 23 Example NAND Gate a z b ECE 448 FPGA and ASIC Design with VHDL a 0 0 1 1 b 0 1 0 1 z 1 1 1 0 24 Example VHDL Code 3 sections to a piece of VHDL code File extension for a VHDL file is vhd Name of the file should be the same as the entity name nand gate vhd OpenCores Coding Guidelines LIBRARY ieee USE ieee std logic 1164 all LIBRARY DECLARATION ENTITY nand gate IS PORT a IN STD LOGIC b IN STD LOGIC z OUT STD LOGIC END nand gate ENTITY DECLARATION ARCHITECTURE model OF nand gate IS BEGIN z a NAND b END model ARCHITECTURE BODY ECE 448 FPGA and ASIC Design with VHDL 25 Design Entity design entity entity declaration architecture 1 architecture 2 Design Entity most basic building block of a design One entity can have many different architectures architecture 3 ECE 448 FPGA and ASIC Design with VHDL 26 Entity Declaration Entity Declaration describes the interface of the component i e input and output ports Entity name Port names Port type ENTITY nand gate IS PORT a IN STD LOGIC b IN STD LOGIC z OUT STD LOGIC END nand gate Reserved words Semicolon No Semicolon after last port Port modes data flow directions ECE 448 FPGA and ASIC Design with VHDL 27 Entity declaration simplified syntax ENTITY entity name IS PORT port name port mode signal type port name port mode signal type port name port mode signal type END entity name ECE 448 FPGA and ASIC Design with VHDL 28 Port Mode IN Port signal Entity a Driver resides outside the entity ECE 448 FPGA
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