ECE 448 Lab 1 Review of Aldec Active HDL Implementing Combinational Logic in VHDL ECE 448 FPGA and ASIC Design with VHDL George Mason University Part 1 Introduction to Aldec Active HDL Example MLU MLU Block Diagram A 0 A1 MUX 0 MUX 4 1 1 NEG A MUX 1 MUX 2 Y1 IN0 IN1 IN2 0 OUTPUT 1 IN3 SEL0 SEL1 NEG Y B 0 B1 L1 L0 1 MUX 3 NEG B Y Experiment 1 Problem 1 ALU of PicoBlaze PicoBlaze Overview 8 bit Register File of PicoBlaze Address 0 7 1 7 7 7 2 3 4 5 6 7 F 7 7 7 s0 s1 s2 s3 s4 s5 s6 s7 7 7 0 0 0 0 0 0 0 0 sF 0 16 Registers Condition Code Registers Flags and its Definition Flags are set or reset after ALU operations Zero flag Z Z 1 0 zero condition if result 0 otherwise Carry flag C overflow underflow or various conditions Example C 1 if 0 result 28 1 or result 0 otherwise Applies only to addition or subtraction related instructions refer to following slides otherwise Syntax and Terminology Syntax Example Definition sX s15 Value at register 15 kk 14 Value 14 PORT kk PORT 2 Input value from port 2 PORT sX PORT S10 Input value from port specified by register 10 RAM kk RAM 4 Value from RAM location 4 Addressing modes Immediate mode ADDCY s2 15 SUB s7 7 s2 15 C s2 s7 7 s7 Direct mode INPUT s10 28 ADD s10 s15 Indirect mode INPUT s9 s2 STORE s3 s10 PORT 28 s10 s10 s15 s10 PORT s2 s9 s3 RAM s10 Assembly language vs machine code Assembly language mnemonic operands Machine code ADDCY s2 16 SUB s7 s8 opcode 1A 1C Value in HEX operands 2 10 7 8 instruction 1A210 1C780 Logic instructions 1 AND AND sX sY sX sY sX AND sX kk sX kk sX 2 OR OR sX sY sX sY sX OR sX kk sX kk sX 3 XOR XOR sX sY sX sY sX XOR sX kk sX kk sX IMM DIR IMM DIR IMM DIR CZ 1 2 Arithmetic Instructions Addition 1 1 ADD sX sY sX sY sX ADD sX kk sX kk sX 1 2 ADDCY sX sY sX sY CARRY sX ADDCY sX kk sX kk CARRY sX Subtraction 2 1 SUB sX sY sX sY sX SUB sX kk sX kk sX 2 2 SUBCY sX sY sX sY CARRY sX SUBCY sX kk sX kk CARRY sX CZ IMM DIR IMM DIR Test and Compare Instructions CZ TEST TEST sX sY sX sY none TEST sX kk sX kk none IMM DIR COMPARE COMPARE sX sY sX sY none COMPARE sX kk sX kk none IMM DIR Data Movement Instructions 1 CZ LOAD LOAD sX sY sY sX LOAD sX kk kk sX STORE STORE sX PP sX RAM PP STORE sX sY sX RAM sY FETCH FETCH sX PP RAM PP sX FETCH sX sY RAM sY sX IMM DIR DIR IND DIR IND Data Movement Instructions 2 CZ INPUT INPUT sX PP sY PORT PP INPUT sX sY sX PORT sY OUTPUT OUTPUT sX PP PORT PP sX OUTPUT sX sY PORT sY sX DIR IND DIR IND Edit instructions Shifts All shift instructions affect Zero and Carry flags Edit instructions Rotations All rotate instructions affect Zero and Carry flags PicoBlaze ALU Instruction Set Summary 1 Instruction 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADD sX kk 0 1 1 0 0 0 x x x x y y y y 0 0 0 0 ADD sX sY 0 1 1 0 0 1 x x x x k k k k k k k k ADDCY sX kk 0 1 1 0 1 0 x x x x y y y y 0 0 0 0 ADDCY sX sY 0 1 1 0 1 1 x x x x k k k k k k k k AND sX kk 0 0 1 0 1 0 x x x x y y y y 0 0 0 0 AND sX sY 0 0 1 0 1 1 x x x x k k k k k k k k COMPARE sX kk 0 1 0 1 0 0 x x x x y y y y 0 0 0 0 COMPARE sX sY 0 1 0 1 0 1 x x x x k k k k k k k k FETCH sX ss 0 0 0 1 1 0 x x x x 0 0 s s s s s s FETCH sX sY 0 0 0 1 1 1 x x x x y y y y 0 0 0 0 INPUT sX sY 0 0 0 1 0 1 x x x x y y y y 0 0 0 0 INPUT sX PP 0 0 0 1 0 0 x x x x p p p p p p p p LOAD sX kk 0 0 0 0 0 0 x x x x k k k k k k k k LOAD sX sY 0 0 0 0 0 1 x x x x y y y y 0 0 0 0 OR sX kk 0 0 1 1 0 0 x x x x k k k k k k k k OR sX sY 0 0 1 1 0 1 x x x x y y y y 0 0 0 0 OUTPUT sX sY 1 0 1 1 0 1 x x x x y y y y 0 0 0 0 OUTPUT sX PP 1 0 1 1 0 0 x x x x p p p p p p p p PicoBlaze ALU Instruction Set Summary 2 Instruction 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RL sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 0 1 0 RR sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 0 0 SL0 sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 1 0 SL1 sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 1 1 SLA sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 0 0 0 SLX sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 0 0 SR0 sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 1 0 SR1 sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 1 1 SRA sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 0 0 0 SRX sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 0 1 …
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