ECE 448 Lecture 19 ASIC Design Flow Sources Jamie Bernard Physical Level Design using Synopsys Scholarly Paper GMU 2005 Cory Ellinger VLSI Design Automation Independent Research Project GMU 2005 Introduction Introduction Technological Advances 19th Century Steel 20th Century Silicon Growth in Microelectronic Silicon Technology Moore s Law of transistors double 18 months One Transistor Small Scale Integration SSI Multiple Devices Transistor Resistor Diodes Possibility to create more than one logic gate Inverter etc Large Scale Integration LSI Systems with at least 1000 logic gates Several thousand transistors Very Large Scale Integration Millions to hundreds of millions of transistors Microprocessors Intel indicates that dual core processors will soon exist that contain 1 billion transistors Introduction Manual Human design can occur with small number of transistors As number of transistors increase through SSI and VLSI the amount of evaluation and decision making would become overwhelming Trade offs Maintaining performance requirements Power Speed Area Design and implementation times become impractical How does one create a complex electronic consisting of millions of transistors Automate the Process using Computer Aided Design CAD Tools Introduction CAD tools provide several advantages Ability to evaluate complex conditions in which solving one problem creates other problems Use analytical methods to assess the cost of a decision Use synthesis methods to help provide a solution Allows the process of proposing and analyzing solutions to occur at the same time Electronic Design Automation Using CAD tools to create complex electronic designs ECAD Several companies who specialize in EDA Cadence Design Systems Magma Design Automation Inc Synopsys CAD Tools Allow Large Problems to be Solved Design Flow Top Level Digital Design Flow Design Inception RTL Design Synthesis Macro Development Place Route Physical Verification Design Complete RTL Design Design Function Digital Tool Design Inception Design Inception RTL Design Cadence NC Verilog Mentor Graphis ModelSim Lint Checking users digression Cadence Hal FPGA Verification users disgression Xilinx ISE Code Coverage users disgression Cadence ICT Testbench Developement Cadence NC Verilog Mentor Graphics ModelSim Mixed Mode Simulation Cadence AMS Designer Formal Verification Cadence Conformal System Interface Simulation Synthesis Synthesis Macro Development Agilent ADS Matlab Synthesis Macro Development Synthesis Macro Development Design Function Digital Tool RTL RTL Synthesis Macro Generation Synopsys DC Cadence RC DFT Macro Verification Synopsys DFT Compiler Cadence RC Mentor Graphics Calibre Macro Rules Generation Library Generation Synopsys PrimeTime Artisan Cadence DFII Static Timing Analysis Logical Equivalency Artisan Cadence Conformal Verification Verification Cadence NC Verilog Mentor Graphics Modelsim Gate Level Simulation Place Route Place Route Place Route Digital Tool Design Function Synthesis Synthesis Floorplan Macro Placement Std Cell Placement Cadence Encounter Placement Based Optimization Clock Tree Synthesis Static Timing Analysis Synopsys PrimeTime Route ATPG Cadence NanoRoute Spare Cells Decoupling Cap Filler Cells RC Extraction Mentor Graphics FastScan Cadence Encounter Cadence Fire Ice QX Signal Integrity Cadence CeltIC Voltage Storm Metal Fill Cadence Encounter Verification Verification Physical Verification Digital Tool Design Function Placed Routed Design Placed Routed Design GDSII Preparation Schematic Preparation Simulation Preparation Cadence DFII Cadence DFII Layout Chip Finishing Back Annotated Simulation Cadence Virtuoso Cadence NC Verilog DRC LVS Mentor Graphics Calibre ERC Top Level Simulation Synopsys Nanosim Cadence AMS Designer Design Complete Design Complete Design Flow Overview Generic VLSI Design Flow from System Specification to Fabrication and Testing Steps prior to Circuit Physical design are part of the FRONT END flow Physical Level Design is part of the BACKEND flow Physical Design is also known as Place and Route CAD tools are involved in all stages of VLSI design flow Different tools can be used at different stages due to EDA common data formats Synopsys CAD tool for Physical Design is called Astro Front End Design Flow Synthesis using Design Compiler Wireload model basics 1 Wireload model basics 2 Back End Design Flow Physical Level Design using Synopsys What does Astro do Where does the Gate Level Netlist come from 1st Input to Astro Standard Cell Library 2nd Input to Astro Pre designed collection of logic functions OR AND XOR etc Contains both Layout and Abstract views Layout CEL contains drawn mask layers required for fabrication Abstract FRAM contains only minimal data needed for Astro Timing information Cell Delay Pin Capacitance Common height for placement purposes Timing Constraints 3rd Input to Astro Derived from system specifications and implementation of design Identical to timing constraints used during logic synthesis Common constraints in electronic designs Clock Speed Frequency Input Output Delays associated with I O signals Multicycle Paths False Paths Astro uses these constraints to consider timing during each stage of the place and route process Concept of Place and Route Location of all standard cells is automatically chosen by the tool during placement Based upon routing and timing Pins are physically connected during routing Based upon timing Concepts of Placement Standard cells are placed in placement rows Cells in a timing critical path are placed close together to reduce routing related delays Timing Driven Placement rows can be abutting or non abutting Concepts of Routing Connecting between metal layers requires one or more vias Metal Layers have preferred routing directions Metal 1 Blue Horizontal Metal 2 Yellow Vertical Metal 3 Red Horizontal Design Setup Design Flow Design Setup The three main inputs for Astro need to be combined into a common database Design Setup needs to be completed prior to performing place and route This environment database allows Astro to use both the logical and physical information of the design Goal of Design Setup is to prepare design for Floorplanning Design Setup Step 1 Creating a Design Library Technology File Layer and via Definitions Process design rules Minimum metal widths and spacing Resistance Capacitance parasitic models Units Time Capacitance Distance GUI display information Colors and fill template for layers This file is
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