Power Management for Wafer Level Test During Burn In Sudarshan Bahukudumbi Intel Corporation Hillsboro Oregon USA Krishnendu Chakrabarty Department of Electrical and Computer Engineering Duke University Durham NC USA Introduction Demand for device reliability and low DPM levels Reliability screening routinely performed before product is shipped Burn in widely used reliability screening method 1 Wafer level test during burn in Wafer level burn in has recently emerged as a promising technique to minimize burn in cost Test during burn in at the wafer level easier and less expensive method to identify faulty devices We refer to this process as wafer level test during burn in WLTBI Increasing demand for known good die highlights need for cost effective WLTBI solutions Comparing Burn In Flows Package level burn in Wafer level test during burn in Wafer Wafer Wafer sort Carrier load WLTBI Wafer dicing Assembly Packaging Assembly Packaging Package test Package test Carrier burn in Optional wafer sort Wafer dicing KGD Assembly Packaging Package burn in Final test Packaged IC Final test Carrier unload KGD Package test Packaged IC 2 Wafer Level Test During Burn In WLTBI AEHR FOX 14 14 simultaneous wafers 30 000 contact point capability Memories Full algorithmic test BIST Vector pattern generator Monitored burn in Motorola teamed up with Tokyo Electron commercial system Similar equipment Advantest and Delta V systems AEHR FOX 14 Full Wafer Contact Burn in and Test System http www aehr com products fox 14 data sheet pdf WLTBI Thermal Challenges Successful WLTBI requires thorough understanding of device thermal characteristics Accurate burn in predictions junction temperatures need to be maintained within a small envelope Junction temperature Tj function of P ambient temperature Ta and thermal resistance ja Tj Ta P ja Controlling power consumption during test is therefore critical for WLTBI K Kanda et al Hitachi IEEE J of Solid State Ckts no 10 pp 1559 1564 Oct 2001 3 Power consumption WLTBI Thermal Challenges Fixed value of device power PBI considered for modeling time required for burn in PBI Under burn in test escape Device subjected to under burn in Results in test escape of latent defects Test time Acceptable margin Power consumption WLTBI Thermal Challenges Fixed value of device power PBI considered for modeling time required for burn in Over burn in yield loss Device subjected to over burn in PBI Results in yield loss Can lead to thermal runaway Need to minimize variance in power consumption Test time Thermal runaway on a packaged 90nm IC Acceptable margin 4 Cycle Accurate Power Consumption Clock Cycle Scan in FF1 FF2 FF3 FF4 FF5 FF6 Scan out 0 1 1 0 1 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 0 2 1 1 0 1 1 0 1 0 1 1 1 3 1 1 0 1 1 0 1 0 1 1 4 1 1 0 1 1 0 1 0 5 1 1 0 1 1 0 1 1 1 0 1 1 0 6 1 0 Number of transitions 45 Cycle by cycle scan cell transitions 4 4 4 4 5 4 Cycle Accurate Power Consumption Test response Ri is shifted out and test pattern Tj is shifted in Test power represented as TC R T TC R T L TC R T TC i j 1 i j n i j R T n 1 i j Average power consumption Ri Tj and statistical variance in test power 2 Ri Tj n 1 R T i R T 2 i j j TC R T k i j k 1 n 1 1 TC R T R T n 1 n 1 k i j i 2 j k 1 5 Metrics Variation In Power Consumption 1 Statistical variance in test power If Ttot is the test time in clock cycles and Pmean the mean value of power consumption per clock cycle the variance is 1 T tot 2 Ttot P P i 2 mean i 1 Cycle to cycle variation Indicator of the flatness in the power profile quantified using P P T count P tc i 1 i i Minimum Variation X Fill Problem PMVF Objective determine X fill values for the test cube and an optimal ordering of test patterns for WLTBI such that Variation in power consumption is minimized Constraint on peak power is satisfied Problem PMVF Given a test set T T1 T2 TN of N test cubes determine appropriate X fill values and an ordering of test patterns such that the a overall variation in power consumption is minimized and b the peak power constraint Pmax is satisfied 6 Proposed Solution Outline Begin Generate test cubes for DUT Generate test cubes for stuck at faults Random ordering considered Eliminate power violations during scan shift Minimum variation X Filling Eliminate power violations during scan capture Eliminating capture power violations Pattern ordering to further reduce variation Pattern Order End Minimum Variation X Filling Clock FF1 FF2 FF3 FF4 Cycle 0 1 2 3 n 1 n r1 r2 t n r1 tn 1 tn tn 2 tn 1 t2 t3 t1 t2 r3 r2 r1 tn t4 t3 r4 r3 r2 r1 t5 t4 FFn 1 FFn rn 1 rn 2 rn 3 rn 4 tn tn 1 rn rn 1 rn 2 rn 3 r1 tn State of flip flops during scan shifting 7 Minimum Variation X Filling Number of transitions per cycle TC 1 r1 tn rn r2 L rn 1 rn 2 rn 1 rn TC 2 tn tn 1 r1 tn L rn 3 rn 2 rn 2 rn 1 M TC n t1 t2 t3 t2 L tn tn 1 r1 tn Change in transition counts per cycle TC 1 TC 2 TC 2 TC 1 t t r r TC 3 TC 3 TC 2 t t r r 0 n 1 n 1 n 1 2 n 1 n 2 n n 1 n 2 M TC n t t r r n 1 1 2 1 2 Minimum Variation X Filling Example Change in transition count for clock cycle j TC j t n j 2 t n j 1 r n j 2 r n j 1 If tn j 1 is a care bit and tn j 2 is unspecified t n j 2 r n j 2 r t1 t2 t3 t4 t5 t6 t7 t8 Response 0 0 0 0 0 0 0 0 Test Cube 1 X X X X 0 X 1 1 0 0 1 1 Vector 0 0 0 Complexity O n n number of eqns n j 1 t n j 1 TC 1 TC 1 TC 2 1 t 0 0 TC 3 t t 0 0 0 1 2 7 7 0 M TC 8 t 1 0 0 7 2 Change in transition counts 8 Eliminating Capture Power Violations Capture power violations excessive transitions during scan capture Capture power Hamming distance test pattern and response If response captured is r r1 r2 rn capture power TC n 1 t r t r L t r 1 1 2 2 n n If TC n …