Unformatted text preview:

1!ECE 538 Krish Chakrabarty 1 ECE 538 VLSI System Testing Krish Chakrabarty System-on-Chip (SOC) Testing ECE 538 Krish Chakrabarty 2 Outline • Motivation for modular testing of SOCs • Wrapper design – IEEE 1500 Standard – Optimization • Test access mechanism design and optimization • Test scheduling • Exploiting port scalability to test embedded cores at multiple data rates – Virtual TAMs – Matching ATE data rates to scan frequencies of embedded cores • Conclusions2!ECE 538 Krish Chakrabarty 3 • System-on-chip (SOC) integrated circuits based on embedded intellectual property (IP) cores are now commonplace – SOCs include processors, memories, peripheral devices, IP cores, analog cores – Low cost, fast time-to-market, high performance, low power – Manufacturing test needed to detect manufacturing defects Motivation Test cost!Manufacturing!cost!ECE 538 Krish Chakrabarty 4 System-on-Chip (SOC) • Test access is limited • Test sets must be transported to embedded logic3!ECE 538 Krish Chakrabarty 5 0 Shorten production cycles, and increasing complexity of modern electronic systems has forced designers to employ reuse based designs approaches. 0 System-on-Chip (SOC) is an example of such reuse based design approach where pre-designed, pre-verified cores are integrated into a system. SOC CPU1 DSP I/O CPU2 RAM RAM TDSP Tests TCPU1 TI/O TCPU2 ECE 538 Krish Chakrabarty 6 IC manufacturing IC testing SOB manufacturing SOC manufacturing SOB testing SOC testing IC design and test development Core design and test development Core provider IC provider SOB design and test development SOC design and test development System integrator System integrator4!ECE 538 Krish Chakrabarty 7 0 Test access mechanism (TAM) 0 An ATE is used to transport the test stimuli to the SOC. The produced responses are transported back to the ATE where they are compared with the expected responses. 0 Memory cores are usually tested using a built-in self-test ATE ATE SOC CPU1 DSP I/O CPU2 RAM RAM TAM Expected test responses Test stimuli Test responses ECE 538 Krish Chakrabarty 8 Modular Testing • Test embedded cores using patterns provided by core vendor (test reuse) • Test access mechanisms (TAMs) needed for test data transport: TAMs impact test time and test cost • Test wrappers translate test data supplied by TAMs • TAM optimization and test scheduling are critical – ITRS 05: Test data volume and testing time in 2010 will 30X that for today’s chips Wrapper Embedded core SOC TAM TAM Automatic Test !Equipment (ATE)!Embedded core Embedded core5!ECE 538 Krish Chakrabarty 9 Test Access Problem 110011010"010010100"101000100"101010000"110011010"010010100"101000100"101010000"110011010"010010100"101000100"101010000"110011010"010010100"101000100"101010000"110011010"010010100"101000100"101010000"110011010"010010100"101000100"101010000"Tester"1. How to isolate cores?"2. How to get patterns to cores?"Plug-and-Play"ECE 538 Krish Chakrabarty 10 Test Scheduling • Test scheduling determines sequence of core tests on the TAMs • Avoid test resource conflicts • Minimize testing time • Ineffective scheduling can increase tester data volume: Idle bits Core 1!Core 2"Core 4"Core 5!Time"Schedule"Idle bits"6!ECE 538 Krish Chakrabarty 11 Test Planning Optimizing test access to cores and scheduling test hardware Core import!Core integration!Test wrapper!& TAM design!Top-level DFT!• Test control blocks!• IEEE 1149.1!Test hardware planning!Core test import!Test assembly!Test scheduling!Top-level ATPG!• Glue logic, soft cores!• Test wrappers!Test software planning!ECE 538 Krish Chakrabarty 12 IEEE 1500 Core Test Standard • Goals – Define test interface between core and SOC – Core isolation – Plug-and-play protocols • Scope – Standardize core isolation protocols and test modes – TAM design – Type of test to be applied – Test scheduling7!ECE 538 Krish Chakrabarty 13 IEEE 1500 Wrapper Wrapper Modes: (1) Normal; (2) Serial Test; (3) 1-N Test; (4) Bypass; (5) Isolation; (6) Extest Marinissen et al., “On IEEE P1500's Standard for Embedded Core Test”, Journal of Electronic Testing: Theory and Applications, vol. 18, Aug 2002 ECE 538 Krish Chakrabarty 14 Wrapper Boundary Cells8!ECE 538 Krish Chakrabarty 15 Wrapper Usage ECE 538 Krish Chakrabarty 16 Wrapped Embedded Cores9!ECE 538 Krish Chakrabarty 17 Wrapper Operation Modes (I) Normal Mode Serial Bypass Mode!ECE 538 Krish Chakrabarty 18 Wrapper Operation Modes (II) Serial Internal Test Mode Serial External Test Mode!10!ECE 538 Krish Chakrabarty 19 Wrapper Operation Modes (III) Parallel Internal Test Mode Parallel External!ECE 538 Krish Chakrabarty 20 Test Wrapper Optimization 4 FF!8 FF!Wrapper!Core"Unbalanced!4 FF!8 FF!Wrapper!Core"Balanced!Minimize length of longest wrapper scan in/out chain Priority 1: Balanced Wrapper Scan Chains11!ECE 538 Krish Chakrabarty 21 Reducing TAM Width Scan chain – 32 FF!8 FF!8 FF!8 FF!I"I"I"I" O"O"4 Wrapper scan chains!Scan chain – 32 FF!I" I" I" I" 8 FF! O" O"8 FF! 8 FF!2 Wrapper scan chains!Priority 2: Minimize wrapper scan chains created ECE 538 Krish Chakrabarty 22 Two-Priority Wrapper Design Algorithm 1. Minimize length of longest wrapper scan in/out chain 2. Minimize number of wrapper scan chains TAM width"Longest wrapper scan chain"Design_wrapper algorithm uses the BFD heuristic for Bin Design12!ECE 538 Krish Chakrabarty 23 Test Access Mechanisms • Multiplexed access [Immaneni, ITC’90] • Reuse system bus [Harrod, ITC’99] • Transparent paths [Ghosh, DAC’98] • Isolation rings [Whetsel, ITC’97] • Test Bus [Varma, ITC’98] • Test Rail [Marinissen, ITC’98] C1" C2" C3"Multi-!plexed!C1" C2" C3"Distri-!bution!Types of TAMs C1" C2" C3"Daisy-!chain!ECE 538 Krish Chakrabarty 24 TAM Design 2. Multiplexing!Core A! Core B!1. Partial isolation rings!13!ECE 538 Krish Chakrabarty 25 TAM Design 3. Core Transparency!Core A! Core B!ECE 538 Krish Chakrabarty 26 Test Bus Architecture A B C D E F Architecture Schedule: Serial • Combination of multiplexing and distribution • Supports only serial schedule • Core-external testing is cumbersome or impossible14!ECE 538 Krish


View Full Document

Duke ECE 269 - VLSI System Testing

Download VLSI System Testing
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view VLSI System Testing and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view VLSI System Testing 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?