ECE 538 VLSI System Testing Krish Chakrabarty System on Chip SOC Testing ECE 538 Krish Chakrabarty 1 Outline Motivation for modular testing of SOCs Wrapper design IEEE 1500 Standard Optimization Test access mechanism design and optimization Test scheduling Exploiting port scalability to test embedded cores at multiple data rates Virtual TAMs Matching ATE data rates to scan frequencies of embedded cores Conclusions ECE 538 Krish Chakrabarty 2 1 Motivation System on chip SOC integrated circuits based on embedded intellectual property IP cores are now commonplace SOCs include processors memories peripheral devices IP cores analog cores Low cost fast time to market high performance low power Manufacturing test needed to detect manufacturing defects Manufacturing cost Test cost ECE 538 Krish Chakrabarty 3 System on Chip SOC Test access is limited Test sets must be transported to embedded logic ECE 538 Krish Chakrabarty 4 2 0Shorten production cycles and increasing complexity of modern electronic systems has forced designers to employ reuse based designs approaches 0System on Chip SOC is an example of such reuse based design approach where pre designed pre verified cores are integrated into a system SOC CPU2 DSP RAM CPU1 I O TDSP TI O TCPU1 TCPU2 Krish Chakrabarty ECE 538 IC design and test development IC provider Tests RAM Core provider 5 Core design and test development IC manufacturing IC testing SOB design and test development System integrator SOB manufacturing SOC design and test development System integrator SOB testing ECE 538 SOC manufacturing SOC testing Krish Chakrabarty 6 3 0Test access mechanism TAM 0An ATE is used to transport the test stimuli to the SOC The produced responses are transported back to the ATE where they are compared with the expected responses 0Memory cores are usually tested using a built in self test Test responses Test stimuli CPU2 RAM Expected test responses RAM TAM ATE DSP CPU1 I O ATE SOC Krish Chakrabarty ECE 538 7 Modular Testing Test embedded cores using patterns provided by core vendor test reuse Test access mechanisms TAMs needed for test data transport TAMs impact test time and test cost Test wrappers translate test data supplied by TAMs TAM optimization and test scheduling are critical ITRS 05 Test data volume and testing time in 2010 will 30X that for today s chips Automatic Test Equipment ATE SOC Embedded core TAM Embedded core Embedded core TAM Wrapper ECE 538 Krish Chakrabarty 8 4 Test Access Problem Plug and Play 110011010 010010100 101000100 101010000 110011010 010010100 101000100 101010000 110011010 010010100 101000100 101010000 110011010 010010100 101000100 101010000 110011010 010010100 101000100 101010000 110011010 010010100 101000100 101010000 Tester 1 How to isolate cores 2 How to get patterns to cores Krish Chakrabarty ECE 538 9 Test Scheduling Schedule Test scheduling determines sequence of core tests on the TAMs Avoid test resource conflicts Minimize testing time Ineffective scheduling can increase tester data volume Idle bits Idle bits Core 1 Core 5 Core 2 Core 4 Time ECE 538 Krish Chakrabarty 10 5 Test Planning Optimizing test access to cores and scheduling test hardware Test hardware planning Test software planning Core import Core integration Test wrapper TAM design Core test import Top level ATPG Glue logic soft cores Test wrappers Test scheduling Top level DFT Test control blocks IEEE 1149 1 ECE 538 Test assembly Krish Chakrabarty 11 IEEE 1500 Core Test Standard Goals Define test interface between core and SOC Core isolation Plug and play protocols Scope Standardize core isolation protocols and test modes TAM design Type of test to be applied Test scheduling ECE 538 Krish Chakrabarty 12 6 IEEE 1500 Wrapper Wrapper Modes 1 Normal 2 Serial Test 3 1 N Test 4 Bypass 5 Isolation 6 Extest Marinissen et al On IEEE P1500 s Standard for Embedded Core Test Journal of Electronic Testing Theory and Applications vol 18 Aug 2002 ECE 538 Krish Chakrabarty 13 Wrapper Boundary Cells ECE 538 Krish Chakrabarty 14 7 Wrapper Usage ECE 538 Krish Chakrabarty 15 Wrapped Embedded Cores ECE 538 Krish Chakrabarty 16 8 Wrapper Operation Modes I Normal Mode ECE 538 Serial Bypass Mode Krish Chakrabarty 17 Wrapper Operation Modes II Serial Internal Test Mode ECE 538 Serial External Test Mode Krish Chakrabarty 18 9 Wrapper Operation Modes III Parallel Internal Test Mode Parallel External Krish Chakrabarty ECE 538 19 Test Wrapper Optimization Priority 1 Balanced Wrapper Scan Chains Core Core 4 FF 4 FF 8 FF 8 FF Wrapper Wrapper Unbalanced Balanced Minimize length of longest wrapper scan in out chain ECE 538 Krish Chakrabarty 20 10 Reducing TAM Width Priority 2 Minimize wrapper scan chains created Scan chain 32 FF I I 8 FF I 8 FF I 8 FF O 4 Wrapper scan chains O 2 Wrapper scan chains Scan chain 32 FF I I I I 8 FF Longest wrapper scan chain 8 FF O O Krish Chakrabarty ECE 538 ECE 538 8 FF 21 Two Priority Wrapper Design Algorithm 1 Minimize length of longest wrapper scan in out chain 2 Minimize number of wrapper scan chains Design wrapper algorithm uses the BFD heuristic for Bin Design TAM width Krish Chakrabarty 22 11 Test Access Mechanisms Types of TAMs Multiplexed access C1 C2 C3 Multi plexed C1 C2 C3 Daisy chain C1 C2 C3 Distri bution Immaneni ITC 90 Reuse system bus Harrod ITC 99 Transparent paths Ghosh DAC 98 Isolation rings Whetsel ITC 97 Test Bus Varma ITC 98 Test Rail Marinissen ITC 98 Krish Chakrabarty ECE 538 23 TAM Design 1 Partial isolation rings 2 Multiplexing Core A ECE 538 Core B Krish Chakrabarty 24 12 TAM Design 3 Core Transparency Core A Core B Krish Chakrabarty ECE 538 25 Test Bus Architecture Architecture A C Schedule Serial B D E F Combination of multiplexing and distribution Supports only serial schedule Core external testing is cumbersome or impossible ECE 538 Krish Chakrabarty 26 13 TestRail Architecture Combination of Daisychain and Distribution architectures Cores connected to a TestRail can be tested simultaneously as well as sequentially Multiple wrappers can be activated simultaneously for Extest TestRails can be either fixed width or flexible width Flexible width TestRails Fixed width TestRails C1 C2 C3 C1 w 1 C2 C3 W C1 C2 C1 w 2 Krish Chakrabarty ECE 538 C2 27 Step by Step Approach to Wrapper TAM Co optimization 1 PW Wrapper design 2 PAW Core assignment PW 3 PPAW TAM width partitioning PAW 4 PNPAW Number of TAMs PPAW W3 W2 W1 ECE 538 TAMs IP IP IP Wrapper Wrapper Wrapper Krish Chakrabarty 28 14 Mathematical Programming Model