1ECE 269Krish Chakrabarty1ECE 269VLSI System TestingKrish ChakrabartyLecture 1:OverviewECE 269Krish Chakrabarty2Lecture 1Introduction• VLSI realization process• Verification and test• Ideal and real tests• Costs of testing• Roles of testing• A modern VLSI device - system-on-a-chip• Course outline– Part I: Introduction to testing– Part II: Test methods– Part III: Design for testabilityClass website: www.ee.duke.edu/~krish/teaching/269.html2ECE 269Krish Chakrabarty3International Technology Roadmap for Semiconductorshttp://public.itrs.net/Files/2003ITRS/Home2003.htm(2005 edition and 2006 update now available)Test costManufacturingcostECE 269Krish Chakrabarty4VLSI Realization ProcessDetermine requirementsWrite specificationsDesign synthesis and VerificationFabricationManufacturing testChips to customerCustomer’s needTest development3ECE 269Krish Chakrabarty5Definitions• Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes.• Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.• Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.ECE 269Krish Chakrabarty6Verification vs. Test • Verifies correctness of design.• Performed by simulation, hardware emulation, or formal methods.• Performed once prior to manufacturing.• Responsible for quality of design.• Verifies correctness of manufactured hardware.• Two-part process:– 1. Test generation: software process executed once during design– 2. Test application: electrical tests applied to hardware• Test application performed on every manufactured device.• Responsible for quality of devices.4ECE 269Krish Chakrabarty7Problems of Ideal Tests• Ideal tests detect all defects produced in the manufacturing process.• Ideal tests pass all functionally good devices.• Very large numbers and varieties of possible defects need to be tested.• Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.ECE 269Krish Chakrabarty8Real Tests• Based on analyzable fault models, which may not map on real defects.• Incomplete coverage of modeled faults due to high complexity.• Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.• Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.5ECE 269Krish Chakrabarty9Testing as a Filter ProcessFabricatedchipsGood chipsDefective chipsProb(good) = yProb(bad) = 1- yProb(pass test) = highProb(fail test) = highProb(failtest) = lowProb(passtest) = lowMostlygoodchipsMostlybadchipsECE 269Krish Chakrabarty10Costs of Testing• Design for testability (DFT)– Chip area overhead and yield reduction– Performance overhead• Software processes of test– Test generation and fault simulation– Test programming and debugging• Manufacturing test– Automatic test equipment (ATE) capital cost– Test center operational cost6ECE 269Krish Chakrabarty11Costs of Testing• Design for testability (DFT)– Chip area overhead and yield reduction– Performance overhead• Software processes of test– Test generation and fault simulation– Test programming and debugging• Manufacturing test– Automatic test equipment(ATE) capital cost– Test center operational cost ECE 269Krish Chakrabarty12Cost of Test• “The emergence of more advanced ICs and SOC semiconductor devices is causing test costs to escalate to as much as 50 percent of the total manufacturing cost.”– M. Kondrat, “Bridging design and ATE cuts test cost - Test & Measurement -automatic test equipment”, Electronic News, Sept 9, 2002.• “As a result, semiconductor test cost continues to increase in spite of the introduction of DFT, and can account for up to 25-50% of total manufacturing cost”. – T. Cooper, G. Flynn, G. Ganesan, R. Nolan, C. Tran, Motorola, “Demonstration and Deployment of a Test Cost Reduction Strategy Using Design-for-Test (DFT) and Wafer Level Burn-In and Test”, (6/29/2001) Future Fab Intl. Volume 11.• “Test may account for more than 70% of the total manufacturing cost - test cost does not directly scale with transistor count, dies size, device pin count, or process technology”, ITRS 2003.7ECE 269Krish Chakrabarty13Motivation: XBox 360 Technical Problems• The "Red Ring of Death": Three red lights on the Xbox 360 indicator, representing "general hardware failure”(http://en.wikipedia.org/wiki/3_Red_Lights_of_Death)• The Xbox 360 can be subject to a number of possible technical problems. Since the Xbox 360 console was released in 2005 the console gained reputation in the press in articles portraying poor reliability and relatively high failure rates.• On 5 July 2007, Peter Moore (Corporate Vice President of the Interactive Entertainment Business in the Entertainment and Devices Division at Microsoft, until August 2007) published an open letter recognizing the problem and announcing 3 years warranty expansion for every Xbox 360 console that experiences the general hardware failure indicated by the three flashing redlights on the console.ECE 269Krish Chakrabarty14XBox 360 Technical Problems (Contd.)• July 5, 2007, Xbox issues to cost Microsoft $1 billion-plus. Unacceptable number of repairs leads to company extending warranties. • Matt Rosoff, an analyst at the independent research group Directions on Microsoft, estimates that Microsoft’s entertainment and devices division has lost more than $6 billion since 2002.8ECE 269Krish Chakrabarty15Roles of Testing• Detection: Determination whether or not the device under test (DUT) has some fault.• Diagnosis: Identification of a specific fault that is present on DUT.• Device characterization: Determination and correction of errors in design and/or test procedure.• Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.ECE 269Krish Chakrabarty16Design for Testability (DFT)DFT refers to hardware design styles or addedhardware that reduces test generation complexity.Motivation: Test generation complexity increasesexponentially with the size of the circuit.Logicblock ALogicblock BPIPOTestinputTestoutputInt.busExample: Test hardware applies tests to blocks Aand B and to internal bus; avoids