ECE 269 VLSI System Testing Krish Chakrabarty Lecture 1 Overview ECE 269 Krish Chakrabarty 1 Lecture 1 Introduction Class website www ee duke edu krish teaching 269 html VLSI realization process Verification and test Ideal and real tests Costs of testing Roles of testing A modern VLSI device system on a chip Course outline Part I Introduction to testing Part II Test methods Part III Design for testability ECE 269 Krish Chakrabarty 2 1 International Technology Roadmap for Semiconductors http public itrs net Files 2003ITRS Home2003 htm 2005 edition and 2006 update now available Manufacturing cost Test cost Krish Chakrabarty ECE 269 3 VLSI Realization Process Customer s need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer ECE 269 Krish Chakrabarty 4 2 Definitions Design synthesis Given an I O function develop a procedure to manufacture a device using known materials and processes Verification Predictive analysis to ensure that the synthesized design when manufactured will perform the given I O function Test A manufacturing step that ensures that the physical device manufactured from the synthesized design has no manufacturing defect Krish Chakrabarty ECE 269 5 Verification vs Test Verifies correctness of design Performed by simulation hardware emulation or formal methods Performed once prior to manufacturing Responsible for quality of design ECE 269 Verifies correctness of manufactured hardware Two part process 1 Test generation software process executed once during design 2 Test application electrical tests applied to hardware Test application performed on every manufactured device Responsible for quality of devices Krish Chakrabarty 6 3 Problems of Ideal Tests Ideal tests detect all defects produced in the manufacturing process Ideal tests pass all functionally good devices Very large numbers and varieties of possible defects need to be tested Difficult to generate tests for some real defects Defect oriented testing is an open problem ECE 269 Krish Chakrabarty 7 Real Tests Based on analyzable fault models which may not map on real defects Incomplete coverage of modeled faults due to high complexity Some good chips are rejected The fraction or percentage of such chips is called the yield loss Some bad chips pass tests The fraction or percentage of bad chips among all passing chips is called the defect level ECE 269 Krish Chakrabarty 8 4 Testing as a Filter Process Good chips Prob good y Prob pass test high Fabricated chips Pr Pr ob fa w il lo t t e tes st low ss pa ob Defective chips Prob bad 1 y Prob fail test high Krish Chakrabarty ECE 269 Mostly good chips Mostly bad chips 9 Costs of Testing Design for testability DFT Chip area overhead and yield reduction Performance overhead Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment ATE capital cost Test center operational cost ECE 269 Krish Chakrabarty 10 5 Costs of Testing Design for testability DFT Chip area overhead and yield reduction Performance overhead Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment ATE capital cost Test center operational cost ECE 269 Krish Chakrabarty 11 Cost of Test The emergence of more advanced ICs and SOC semiconductor devices is causing test costs to escalate to as much as 50 percent of the total manufacturing cost M Kondrat Bridging design and ATE cuts test cost Test Measurement automatic test equipment Electronic News Sept 9 2002 As a result semiconductor test cost continues to increase in spite of the introduction of DFT and can account for up to 25 50 of total manufacturing cost T Cooper G Flynn G Ganesan R Nolan C Tran Motorola Demonstration and Deployment of a Test Cost Reduction Strategy Using Design for Test DFT and Wafer Level Burn In and Test 6 29 2001 Future Fab Intl Volume 11 Test may account for more than 70 of the total manufacturing cost test cost does not directly scale with transistor count dies size device pin count or process technology ITRS 2003 ECE 269 Krish Chakrabarty 12 6 Motivation XBox 360 Technical Problems The Red Ring of Death Three red lights on the Xbox 360 indicator representing general hardware failure http en wikipedia org wiki 3 Red Lights of Death The Xbox 360 can be subject to a number of possible technical problems Since the Xbox 360 console was released in 2005 the console gained reputation in the press in articles portraying poor reliability and relatively high failure rates On 5 July 2007 Peter Moore Corporate Vice President of the Interactive Entertainment Business in the Entertainment and Devices Division at Microsoft until August 2007 published an open letter recognizing the problem and announcing 3 years warranty expansion for every Xbox 360 console that experiences the general hardware failure indicated by the three flashing red lights on the console ECE 269 Krish Chakrabarty 13 XBox 360 Technical Problems Contd July 5 2007 Xbox issues to cost Microsoft 1 billion plus Unacceptable number of repairs leads to company extending warranties Matt Rosoff an analyst at the independent research group Directions on Microsoft estimates that Microsoft s entertainment and devices division has lost more than 6 billion since 2002 ECE 269 Krish Chakrabarty 14 7 Roles of Testing Detection Determination whether or not the device under test DUT has some fault Diagnosis Identification of a specific fault that is present on DUT Device characterization Determination and correction of errors in design and or test procedure Failure mode analysis FMA Determination of manufacturing process errors that may have caused defects on the DUT ECE 269 Krish Chakrabarty 15 Design for Testability DFT DFT refers to hardware design styles or added hardware that reduces test generation complexity Motivation Test generation complexity increases exponentially with the size of the circuit Example Test hardware applies tests to blocks A and B and to internal bus avoids test generation for combined A and B blocks Int Logic Logic bus PI block A block B Test input ECE 269 PO Test output Krish Chakrabarty 16 8 Cost of Manufacturing Testing 0 5 1 0GHz analog instruments 1 024 digital pins ATE purchase price 1 2M 1 024 x 3 000 4 272M Running cost five year linear depreciation Depreciation Maintenance Operation 0 854M 0 085M 0 5M 1