1ECE 269Krish Chakrabarty1ECE 269VLSI System TestingKrish ChakrabartyLecture 12:Sequential Circuit ATPG-2ECE 269Krish Chakrabarty2Introduction• Gate-level test generation– Topological analysis methods– Simulation-based– Genetic algorithms• Test compaction– Static compaction– Dynamic compaction• High-level test generation2ECE 269Krish Chakrabarty3Extended D-Algorithmx1zyx2• Start with time frame 0• Propagate error to primary output by forward time processing• Justify state by reverse time processingx1zyx2x1zyx2Time frame 0 Time frame 1Time frame -1101s-a-0s-a-0s-a-010DDD010Test sequence: (x1,x2) = {(X,0),(1,1),(X,1)}ECE 269Krish Chakrabarty49-Valued Logicx1zyx2Time frame -11s-a-00x1yx2Time frame 00s-a-01z110DD01Contradictionx1zyx2Time frame -1x1yx2Time frame 0zs-a-05-valuedlogic1/00/10/X1/X0/X1/0s-a-00/X1/11/X1/X9-valuedlogic1/X0/XTestfound3ECE 269Krish Chakrabarty5State Justification Decision TreeStartGoal: Make all state variables XUntriedalternativesAlready visitedStopAn example withtwo flip-flops(y1,y2)(0,1)(X,1)(0,1)(1,1)(X,X)SUCCESSStopUntriedalternatives• Keep track of statesalready visitedECE 269Krish Chakrabarty6Simulation-Based ATPG: Motivation• Difficulties with time-frame method:• Long initialization sequence• Impossible initialization with three-valued logic (Section 5.3.4)• Circuit modeling limitations• Timing problems – tests can cause races/hazards• High complexity• Inadequacy for asynchronous circuits• Advantages of simulation-based methods• Advanced fault simulation technology• Accurate simulation model exists for verification• Variety of tests – functional, heuristic, random• Used since early 1960s4ECE 269Krish Chakrabarty7Simulation-Based ATPG• Genetic algorithms• Advantages: less CPU time than ILA model methods• Disadvantages: cannot identify undetectable faults, longer test sequences– Biologically-inspired– Initial population (test sequences), perform selection, mutation, and crossoveroperations– Fitness function used• Challenge: How to determine fitness function?ECE 269Krish Chakrabarty8Using Fault SimulatorYesYesYesYesFaultsimulatorVector source:Functional (test-bench),Heuristic (walking 1, etc.),Weighted random,randomFaultlistTestvectorsNew faultsdetected?Stoppingcriteria(faultcoverage, CPUtime limit, etc.)satisfied?StopUpdatefaultlistAppendvectorsRestorecircuitstateGeneratenew trialvectorsYes Yes Yes Yes NoNoNoNoNoNoNoNoTrial
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