1 ECE 269 Krish Chakrabarty 1 ECE 269VLSI System TestingKrish ChakrabartyBuilt-In Self-Test (BIST): 1ECE 269 Krish Chakrabarty 2 BIST Motivation • Useful for field test and diagnosis (less expensive than a local automatic test equipment) • Software tests for field test and diagnosis:  Low hardware fault coverage  Low diagnostic resolution  Slow to operate • Hardware BIST benefits:  Lower system test effort  Improved system maintenance and repair  Improved component repair  Better diagnosis2 ECE 269 Krish Chakrabarty 3 Costly Test Problems Alleviated by BIST • Increasing chip logic-to-pin ratio – harder observability • Increasingly dense devices and faster clocks • Increasing test generation and application times • Increasing size of test vectors stored in ATE • Expensive ATE needed for multi-GHz chips • Hard testability insertion – designers unfamiliar with gate-level logic, since they design at behavioral level • Shortage of test engineers • Circuit testing cannot be easily partitioned ECE 269 Krish Chakrabarty 4 Typical Quality Requirements • 98% single stuck-at fault coverage • 100% interconnect fault coverage • Reject ratio (DPM) – 1 in 100,000 Example:3 ECE 269 Krish Chakrabarty 5 Design and test + / - + / - + / - Fabri- cation + + + Manuf. Test - - - Level Chips Boards System Maintenance test - Diagnosis and repair - - Service interruption - + Cost increase - Cost saving +/- Cost increase may balance cost reduction Benefits and Costs of BIST with DFT ECE 269 Krish Chakrabarty 6 Economics – BIST Costs  Chip area overhead for: • Test controller • Hardware pattern generator • Hardware response compacter • Testing of BIST hardware  Pin overhead -- At least 1 pin needed to activate BIST operation  Performance overhead – extra path delays due to BIST  Yield loss – due to increased chip area or more chips in system because of BIST  Reliability reduction – due to increased area  Increased BIST hardware complexity – happens when BIST hardware is made testable4 ECE 269 Krish Chakrabarty 7 BIST Benefits • Faults tested:  Single combinational / sequential stuck-at faults  Delay faults  Single stuck-at faults in BIST hardware • BIST benefits  Reduced testing and maintenance cost  Lower test generation cost  Reduced storage / maintenance of test patterns  Simpler and less expensive ATE  Can test many units in parallel  Shorter test application times  Can test at functional system speed ECE 269 Krish Chakrabarty 8 Some Definitions • BILBO – Built-in logic block observer, extra hardware added to flip-flops so they can be reconfigured as an LFSR pattern generator or response compacter, a scan chain, or as flip-flops • Concurrent testing – Testing process that detects faults during normal system operation • CUT – Circuit-under-test • Exhaustive testing – Apply all possible 2n patterns to a circuit with n inputs • Irreducible polynomial – Boolean polynomial that cannot be factored • LFSR – Linear feedback shift register, hardware that generates pseudo-random pattern sequence5 ECE 269 Krish Chakrabarty 9 More Definitions • Primitive polynomial – must divide the polynomial 1 + xk for k = 2n – 1, but not for any smaller k value • Pseudo-exhaustive testing – Break circuit into small, overlapping blocks and test each exhaustively • Pseudo-random testing – Algorithmic pattern generator that produces a subset of all possible tests with most of the properties of randomly-generated patterns • Signature – Any statistical circuit property distinguishing between bad and good circuits • TPG – Hardware test pattern generator ECE 269 Krish Chakrabarty 10 BIST Process • Test controller – Hardware that activates self-test simultaneously on all PCBs • Each board controller activates parallel chip • BIST Diagnosis effective only if very high fault coverage6 ECE 269 Krish Chakrabarty 11 BIST Architecture • Note: BIST cannot test wires and transistors:  From PI pins to Input MUX  From POs to output pins ECE 269 Krish Chakrabarty 12 BILBO – Works as Both a PG and a RC • Built-in Logic Block Observer (BILBO) -- 4 modes: 1. Flip-flop 2. LFSR pattern generator 3. LFSR response compacter 4. Scan chain for flip-flops7 ECE 269 Krish Chakrabarty 13 Complex BIST Architecture • Testing epoch I:  LFSR1 generates tests for CUT1 and CUT2  BILBO2 (LFSR3) compacts CUT1 (CUT2) • Testing epoch II:  BILBO2 generates test patterns for CUT3  LFSR3 compacts CUT3 response ECE 269 Krish Chakrabarty 14 Bus-Based BIST Architecture • Self-test control broadcasts patterns to each CUT over bus – parallel pattern generation • Awaits bus transactions showing CUT’s responses to the patterns: serialized compaction8 ECE 269 Krish Chakrabarty 15 Pattern Generation • Store in ROM – too expensive • Exhaustive • Pseudo-exhaustive • Pseudo-random (LFSR) – Preferred method • Binary counters – use more hardware than LFSR • Modified counters • Test pattern augmentation  LFSR combined with a few patterns in ROM  Hardware diffracter – generates pattern cluster in neighborhood of pattern stored in ROM ECE 269 Krish Chakrabarty 16 Exhaustive Pattern Generation • Shows that every state and transition works • For n-input circuits, requires all 2n vectors • Impractical for n > 209 ECE 269 Krish Chakrabarty 17 Pseudo-Exhaustive Method  Partition large circuit into fanin cones  Backtrace from each PO to PIs influencing it  Test fanin cones in parallel  Reduced # of tests from 28 = 256 to 25 x 2 = 64  Incomplete fault coverage ECE 269 Krish Chakrabarty 18 Pseudo-Exhaustive Pattern Generation10 ECE 269 Krish Chakrabarty 19 Random Pattern Testing Bottom: random-pattern resistant circuit ECE 269 Krish Chakrabarty 20 Pseudo-Random Pattern Generation • Standard Linear Feedback Shift Register (LFSR)  Produces patterns algorithmically – repeatable  Has most of desirable random # properties • Need not cover all 2n input combinations • Long sequences needed for good fault