ECE 269 VLSI System Testing Krish Chakrabarty Lecture 21 Delay Test Part 1 ECE 269 Krish Chakrabarty 1 Delay Test Delay test definition Circuit delays and event propagation Path delay tests Non robust test Robust test Five valued logic and test generation Path delay fault PDF and other fault models Test application methods Combinational enhanced scan and normal scan Variable clock and rated clock methods At speed test Timing design and delay test Summary ECE 269 Krish Chakrabarty 2 1 Delay Test Definition A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing For a combinational or synchronous sequential circuit delay test verifies the limits of delay in combinational logic Delay test problem for asynchronous circuits is complex and not well understood Krish Chakrabarty ECE 269 3 Digital Circuit Timing Input Signal changes Synchronized With clock Outputs Comb logic Transient region Inputs Output Observation instant Clock period ECE 269 Krish Chakrabarty time 4 2 Circuit Delays Switching or inertial delay is the interval between input change and output change of a gate Depends on input capacitance device transistor characteristics and output capacitance of gate Also depends on input rise or fall times and states of other inputs second order effects Approximation fixed rise and fall delays or min max delay range or single fixed delay for gate output Propagation or interconnect delay is the time a transition takes to travel between gates Depends on transmission line effects distributed R L C parameters length and loading of routing paths Approximation modeled as lumped delays for gate inputs See Section 5 3 5 for timing models Krish Chakrabarty ECE 269 5 Event Propagation Delays Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew Path P1 1 0 13 P2 0 0 ECE 269 2 1 3 246 P3 5 2 Krish Chakrabarty 6 3 Circuit Outputs Each path can potentially produce one signal transition at the output The location of an output transition in time is determined by the delay of the path Clock period Final value Initial value Fast transitions Slow transitions time Initial value ECE 269 Final value Krish Chakrabarty 7 Singly Testable Paths Non Robust Test The delay of a target path is tested if the test propagates a transition via path to a path destination Delay test is a combinational vector pair V1 V2 that Produces a transition at path input Produces static sensitization All off path inputs assume non don t care V1 V2 controlling states in V2 Off path inputs V1 V2 Target path Static sensitization guarantees a test when the target path is the only faulty path The test is therefore called non robust It is a test with minimal restriction A path with no such test is a false path ECE 269 Krish Chakrabarty 8 4 Robust Test A robust test guarantees the detection of a delay fault of the target path irrespective of delay faults on other paths A robust test is a combinational vector pair V1 V2 that satisfies following conditions Produce real events different steady state values for V1 and V2 on all on path signals All on path signals must have controlling events arriving via the target path A robust test is also a non robust test Concept of robust test is general robust tests for other fault models can be defined ECE 269 Krish Chakrabarty 9 Path Delay Faults PDF Two PDFs rising and falling transitions for each physical path Total number of paths is an exponential function of gates Critical paths identified by static timing analysis e g Primetime from Synopsys must be tested PDF tests are delay independent Robust tests are preferred but some paths have only non robust tests ECE 269 Krish Chakrabarty 10 5 Other Delay Fault Models Segment delay fault A segment of an I O path is assumed to have large delay such that all paths containing the segment become faulty Transition fault A segment delay fault with segment of unit length single gate Two faults per gate slow to rise and slow to fall Tests are similar to stuck at fault tests For example a line is initialized to 0 and then tested for s a 0 fault to detect slow to rise transition fault Models spot or gross delay defects Line delay fault A transition fault tested through the longest delay path Two faults per line or gate Tests are dependent on modeled delays of gates Gate delay fault A gate is assumed to have a delay increase of certain amount called fault size while all other gates retain some nominal delays Gate delay faults only of certain sizes may be detectable Krish Chakrabarty ECE 269 11 Slow Clock Test Input latches Combinational circuit Input test clock Test clock period Input test clock Rated clock period Output latches Output test clock Output test clock V1 applied ECE 269 V2 applied Output latched Krish Chakrabarty 12 6 Enhanced Scan Test CK period Combinational PO CK circuit SCANOUT CK TC HL HOLD HOLD SFF HL SFF Scanout result V1 settles SCANIN Scan mode TC CK TC CK system clock TC test control HOLD hold signal SFF scan flip flop HL hold latch Normal mode PI Scanin V1 states V1 PI applied Scanin V2 states Result latched V2 PI applied Krish Chakrabarty ECE 269 13 Normal Scan Test V2 states generated A by one bit scan shift of V1 or B by V1 applied in functional mode Combinational CK TC Slow clock SFF TC A SFF CK TC Slow CK period TC B Scan mode Krish Chakrabarty Path tested Result scanout t Rated CK period Scan mode SCANIN CK system clock TC test control SFF scan flip flop ECE 269 V2 PIs applied Scanin Gen V2 V1 states states circuit SCANOUT V1 PIs applied PO Normal mode PI Result latched Normal mode Scan mode Scan mode 14 7 Variable Clock Sequential Test Off path flip flop PI PI PI 0 T 1 T n 2 1 PO PI PI 1 T n 1 2 PO PI PO Initialization sequence slow clock 1 T n 1 2 2 0 D PO Path activation rated Clock T n 1 PO T n m PO Fault effect propagation sequence slow clock Note Slow clock makes the circuit fault free in the presence of delay faults ECE 269 Krish Chakrabarty 15 Variable Clock Models Fault effect propagation can be affected by ambiguous states of off path flip flops at the end of the rated clock time frame Fault model A Off path flip flops assumed to be in correct states sequential non robust test optimistic Fault model B Off path flip flops assumed to be in unknown state sequential robust test pessimistic Fault model C Off path flip flops in steady hazard free state retain their correct values while others assume unknown