ECE 269 VLSI System Testing Krish Chakrabarty Logic Simulation Krish Chakrabarty ECE 269 1 Introduction Motivation Types of logic simulation Compiled code Event driven Delay models Element evaluation Hazard detection ECE 269 Krish Chakrabarty 2 1 Motivation A design verification technique functional and timing Compare results obtained with expected responses specified by the specification Use software model Stimuli and control Simulation program Results Internal model ECE 269 Krish Chakrabarty 3 Motivation Correctness independent of initial power on state Insensitive to small variations in component delays Free of races oscillations illegal input combinations unsafe states Evaluation of design alternatives what if scenarios Documentation generation of timing diagrams ECE 269 Krish Chakrabarty 4 2 Logic Simulation What is simulation Design verification Circuit modeling True value simulation algorithms Compiled code simulation Event driven simulation Summary Krish Chakrabarty ECE 269 5 Simulation Defined Definition Simulation refers to modeling of a design its function and performance A software simulator is a computer program an emulator is a hardware simulator Simulation is used for design verification Validate assumptions Verify logic Verify performance timing Types of simulation ECE 269 Logic or switch level Timing Circuit Fault Krish Chakrabarty 6 3 Simulation for Verification Specification Synthesis Response analysis Design changes Design netlist True value simulation Computed responses ECE 269 Input stimuli Krish Chakrabarty 7 Modeling for Simulation Modules blocks or components described by Input output I O function Delays associated with I O signals Examples binary adder Boolean gates FET resistors and capacitors Interconnects represent ideal signal carriers or ideal electrical conductors Netlist a format or language that describes a design as an interconnection of modules Netlist may use hierarchy ECE 269 Krish Chakrabarty 8 4 Example A Full Adder HA inputs a b outputs c f AND A1 a b c AND A2 d e f OR O1 a b d NOT N1 c e c a e d f b HA A HA1 B C D E Carry F HA2 ECE 269 Sum FA inputs A B C outputs Carry Sum HA HA1 A B D E HA HA2 E C F Sum OR O2 D F Carry Krish Chakrabarty 9 Logic Model of MOS Circuit pMOS FETs VDD a a Ca c b Cc b Cb nMOS FETs Ca Cb and Cc are parasitic capacitances ECE 269 Krish Chakrabarty Da Dc c Db Da and Db are interconnect or propagation delays Dc is inertial delay of gate 10 5 Options for Inertial Delay simulation of a NAND gate Transient region Inputs a b c CMOS Logic simulation c zero delay c unit delay X c multiple delay rise 5 fall 5 Unknown X c minmax delay min 2 max 5 Time units 5 0 Krish Chakrabarty ECE 269 11 Signal States Two states 0 1 can be used for purely combinational logic with zero delay Three states 0 1 X are essential for timing hazards and for sequential logic initialization Four states 0 1 X Z are essential for MOS devices See example below Analog signals are used for exact timing of digital logic and for analog circuits Z hold previous value 0 0 ECE 269 Krish Chakrabarty 12 6 Modeling Levels Modeling level Timing Application 0 1 Clock boundary Architectural and functional verification 0 1 X and Z Zero delay unit delay multipledelay Logic verification and test Transistor size and connectivity node capacitances 0 1 and X Zero delay Logic verification Transistor technology data connectivity node capacitances Analog voltage Fine grain timing Timing verification Tech Data active passive component connectivity Analog voltage current Continuous time Digital timing and analog circuit verification Circuit description Programming Function language like HDL behavior RTL Logic Switch Timing Circuit ECE 269 Connectivity of Boolean gates flip flops and transistors Signal values Krish Chakrabarty 13 True Value Simulation Algorithms Compiled code simulation oblivious simulation Applicable to zero delay combinational logic Also used for cycle accurate synchronous sequential circuits for logic verification Efficient for highly active circuits but inefficient for lowactivity circuits High level e g C language models can be used Event driven simulation exclusive simulation of activity Only gates or modules with input events are evaluated event means a signal change Delays can be accurately simulated for timing verification Efficient for low activity circuits Can be extended for fault simulation ECE 269 Krish Chakrabarty 14 7 Types of Simulation Contd Compiled code oblivious The circuit is described in a programming language and an executable model is generated Circuit operation program execution Fast and efficient but inflexible practical only for small circuits Event driven Exclusive simulation of activity Circuit is a data structure simulation program is same for all circuits Flexible but requires event list management overhead ECE 269 Krish Chakrabarty 15 Compiled Code Algorithm Step 1 Levelize combinational logic and encode in a compilable programming language Step 2 Initialize internal state variables flip flops Step 3 For each input vector Set primary input variables Repeat until steady state or max iterations Execute compiled code Report or save computed variables ECE 269 Krish Chakrabarty 16 8 Compiled Code Simulation LDA B AND Q INV STA E OR A STA F STA Q F A B E D C Q Simulation program Delays can be modeled by explicitly adding them to the software model ECE 269 Krish Chakrabarty 17 Event Driven Simulation Advance simulation time No more events Done Determine current events Update values Propagate events Evaluate activated elements Schedule resulting events ECE 269 Krish Chakrabarty 18 9 Event Driven Simulation A 0 G 2 B 1 2 C 1 0 at t 0 0 F E 0 D 2 0 3 0 Y 1 0Z Snapshot of event list t 0 Event Time F 1 t 2 t 2 Event Time G 1 t 4 Z 1 t 4 t 4 Event Time Y 1 t 7 Krish Chakrabarty ECE 269 19 Event Driven Algorithm Example t 0 e 1 2 0 g 1 2 4 f 0 2 4 4 f g 8 g 0 5 f 1 g 7 Time t 8 ECE 269 d 1 e 0 3 6 g 0 d e 2 d 0 b 1 c 0 1 Time stack a 1 c 1 Scheduled Activity events list Krish Chakrabarty g 1 20 10 Time Wheel Circular Stack max Current time pointer t 0 1 Event link list 2 3 4 5 6 7 Krish Chakrabarty ECE 269 21 Efficiency of Event driven Simulator Simulates events value changes only Speed up over compiled code can be ten times or more in large logic circuits about 0 1 to 10 gates become active for an input change Steady 0 0 to 1 event ECE 269 Steady 0 no event Krish Chakrabarty Large logic block without activity 22 11 Delay Models