1ECE 269Krish Chakrabarty1ECE 269VLSI System TestingKrish ChakrabartyLogic SimulationECE 269Krish Chakrabarty2Introduction• Motivation• Types of logic simulation– Compiled code– Event-driven• Delay models• Element evaluation• Hazard detection2ECE 269Krish Chakrabarty3Motivation• A design verification technique (functional and timing)• Compare results obtained with expected responses specified by the specification• Use software modelSimulationprogramStimuliandcontrolInternalmodelResultsECE 269Krish Chakrabarty4Motivation• Correctness, independent of initial (power-on) state• Insensitive to small variations in component delays• Free of races, oscillations, “illegal” input combinations, “unsafe” states• Evaluation of design alternatives (what-if scenarios)• Documentation (generation of timing diagrams)3ECE 269Krish Chakrabarty5Logic Simulation• What is simulation?• Design verification• Circuit modeling• True-value simulation algorithms• Compiled-code simulation• Event-driven simulation•SummaryECE 269Krish Chakrabarty6Simulation Defined• Definition: Simulation refers to modeling of a design, its function and performance.• A software simulator is a computer program; an emulator is a hardware simulator.• Simulation is used for design verification:• Validate assumptions• Verify logic• Verify performance (timing)• Types of simulation:• Logic or switch level• Timing•Circuit•Fault4ECE 269Krish Chakrabarty7Simulation for VerificationTrue-valuesimulationSpecificationDesign(netlist)Input stimuliComputedresponsesResponseanalysisSynthesisDesignchangesECE 269Krish Chakrabarty8Modeling for Simulation• Modules, blocks or components described by• Input/output (I/O) function• Delays associated with I/O signals• Examples: binary adder, Boolean gates, FET, resistors and capacitors• Interconnects represent• ideal signal carriers, or• ideal electrical conductors• Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy.5ECE 269Krish Chakrabarty9Example: A Full-AdderHA; inputs: a, b;outputs: c, f;AND: A1, (a, b), (c);AND: A2, (d, e), (f);OR: O1, (a, b), (d);NOT: N1, (c), (e);a bcd e f HA FA;inputs: A, B, C;outputs: Carry, Sum;HA: HA1, (A, B), (D, E);HA: HA2, (E, C), (F, Sum);OR: O2, (D, F), (Carry);HA1HA2AB C D E F Sum Carry ECE 269Krish Chakrabarty10Ca Logic Model of MOS CircuitCc CbVDD a b c pMOS FETsnMOS FETsCa , Cband Cc are parasitic capacitancesDcDacab Daand Dbare interconnect or propagation delaysDcis inertial delayof gateDb6ECE 269Krish Chakrabarty11Options for Inertial Delay(simulation of a NAND gate)b ac (CMOS)Time units05c (zero delay)c (unit delay)c (multiple delay)c (minmax delay)InputsLogic simulationmin =2, max =5rise=5, fall=5Transient region Unknown (X)XECE 269Krish Chakrabarty12Signal States• Two-states (0, 1) can be used for purely combinational logic with zero-delay.• Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization.• Four-states (0, 1, X, Z) are essential for MOS devices. See example below.• Analog signals are used for exact timing of digital logic and for analog circuits.00Z(hold previous value)7ECE 269Krish Chakrabarty13Modeling LevelsCircuitdescriptionProgramminglanguage-like HDLConnectivity ofBoolean gates,flip-flops andtransistorsTransistor sizeand connectivity,node capacitancesTransistor technologydata, connectivity,node capacitancesTech. Data, active/passive componentconnectivitySignalvalues0, 10, 1, Xand Z0, 1and XAnalogvoltageAnalogvoltage,currentTimingClockboundaryZero-delayunit-delay,multiple-delayZero-delayFine-graintimingContinuoustimeModelinglevelFunction,behavior, RTLLogicSwitchTimingCircuitApplicationArchitecturaland functionalverificationLogicverificationand testLogicverificationTimingverificationDigital timingand analogcircuitverificationECE 269Krish Chakrabarty14True-Value Simulation Algorithms• Compiled-code simulation (oblivious simulation)• Applicable to zero-delay combinational logic• Also used for cycle-accurate synchronous sequential circuits for logic verification• Efficient for highly active circuits, but inefficient for low-activity circuits• High-level (e.g., C language) models can be used• Event-driven simulation (exclusive simulation of activity)• Only gates or modules with input events are evaluated (event means a signal change)• Delays can be accurately simulated for timing verification• Efficient for low-activity circuits• Can be extended for fault simulation8ECE 269Krish Chakrabarty15Types of Simulation (Contd.)• Compiled-code (oblivious)– The circuit is described in a programming language and an executable model is generated– Circuit operation ≡ program execution– Fast and efficient but inflexible; practical only for small circuits• Event-driven– Exclusive simulation of activity– Circuit is a data structure, simulation program is same for all circuits– Flexible, but requires event list management (overhead)ECE 269Krish Chakrabarty16Compiled-Code Algorithm• Step 1: Levelize combinational logic and encode in a compilable programming language• Step 2: Initialize internal state variables (flip-flops)• Step 3: For each input vector– Set primary input variables– Repeat (until steady-state or max. iterations)• Execute compiled code– Report or save computed variables9ECE 269Krish Chakrabarty17Compiled-Code SimulationDCQBAEFLDA BAND QINVSTA EOR ASTA FSTA QSimulation program• Delays can be modeled by explicitly addingthem to the software modelECE 269Krish Chakrabarty18Event-Driven SimulationAdvance simulation timeDetermine current eventsUpdate valuesPropagate eventsEvaluate activated elementsSchedule resulting eventsDoneNo more events10ECE 269Krish Chakrabarty19Event-Driven SimulationBAEF22CDZ01 → 0at t = 01001Event TimeF = 1 t = 2t = 0Snapshot of event listEvent TimeG = 1 t = 4Z = 1 t = 4t = 2Event TimeY = 1 t = 7t = 432YG000ECE 269Krish Chakrabarty20Event-Driven Algorithm(Example)2242a =1b =1c =1 0d = 0e =1f =0g =1Time, t048gt = 0 12345678Scheduledeventsc = 0d = 1, e = 0g = 0f = 1g = 1Activitylistd, ef, ggTime stack11ECE 269Krish Chakrabarty21Time Wheel (Circular Stack)t=01234567maxCurrenttimepointerEvent link-listECE 269Krish Chakrabarty22Efficiency of Event-driven Simulator• Simulates events (value changes) only• Speed up over